Simulation Results: alert_handler

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.04 %
  • code
  • 91.18 %
  • assert
  • 98.47 %
  • func
  • 80.47 %
  • line
  • 99.74 %
  • branch
  • 98.31 %
  • cond
  • 90.48 %
  • toggle
  • 89.94 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 19.490s 602.965us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 10.260s 155.032us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.450s 24.251us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 351.110s 30690.349us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 66.390s 3254.876us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 16.220s 364.113us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.450s 24.251us 1 1 100.00
alert_handler_csr_aliasing 66.390s 3254.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 204.530s 2772.878us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 24.290s 318.763us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1712.290s 118329.099us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 18.420s 271.266us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 19.490s 602.965us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 95.610s 1486.367us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 6.300s 67.557us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 343.600s 37572.321us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1931.740s 37483.630us 1 1 100.00
alert_handler_lpg_stub_clk 2946.620s 223007.092us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1869.530s 18947.593us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.130s 382.989us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 5.150s 231.425us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.000s 18.314us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.100s 213.865us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.100s 213.865us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 10.260s 155.032us 1 1 100.00
alert_handler_csr_rw 3.450s 24.251us 1 1 100.00
alert_handler_csr_aliasing 66.390s 3254.876us 1 1 100.00
alert_handler_same_csr_outstanding 31.110s 1556.770us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 10.260s 155.032us 1 1 100.00
alert_handler_csr_rw 3.450s 24.251us 1 1 100.00
alert_handler_csr_aliasing 66.390s 3254.876us 1 1 100.00
alert_handler_same_csr_outstanding 31.110s 1556.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 457.730s 11710.678us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 457.730s 11710.678us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 457.730s 11710.678us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 457.730s 11710.678us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 790.530s 33187.312us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
alert_handler_tl_intg_err 110.930s 5441.531us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 110.930s 5441.531us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 457.730s 11710.678us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 19.490s 602.965us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 19.490s 602.965us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 19.490s 602.965us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 19.490s 602.965us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 18.420s 271.266us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1931.740s 37483.630us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 18.420s 271.266us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1712.290s 118329.099us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1712.290s 118329.099us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 13.960s 252.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 149.680s 23310.799us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 7974492894929809963675260280210534253889200877226671500246955049919939028656 154
UVM_INFO @ 382989489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 88692418366468279334873675276601171636310000980443350967179842137921375729045 123
UVM_INFO @ 23310798542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---