Simulation Results: clkmgr

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.66 %
  • code
  • 69.47 %
  • assert
  • 90.29 %
  • func
  • 67.21 %
  • line
  • 82.37 %
  • branch
  • 87.53 %
  • cond
  • 79.36 %
  • toggle
  • 98.11 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.280s 30.963us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 2.360s 131.662us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.130s 15.305us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 5.790s 409.928us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.890s 2.384us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 2.430s 113.819us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 1.130s 15.305us 1 1 100.00
clkmgr_csr_aliasing 0.890s 2.384us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.800s 92.096us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.440s 27.559us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.330s 30.820us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.280s 30.963us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.920s 6.766us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.960s 6.069us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.920s 6.766us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 4.730s 464.940us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.190s 18.418us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.870s 39.848us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.870s 39.848us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 2.360s 131.662us 1 1 100.00
clkmgr_csr_rw 1.130s 15.305us 1 1 100.00
clkmgr_csr_aliasing 0.890s 2.384us 0 1 0.00
clkmgr_same_csr_outstanding 1.190s 22.023us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 2.360s 131.662us 1 1 100.00
clkmgr_csr_rw 1.130s 15.305us 1 1 100.00
clkmgr_csr_aliasing 0.890s 2.384us 0 1 0.00
clkmgr_same_csr_outstanding 1.190s 22.023us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 16.580s 1482.148us 1 1 100.00
clkmgr_tl_intg_err 1.060s 6.937us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 3.020s 191.164us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 3.020s 191.164us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 3.020s 191.164us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 3.020s 191.164us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.990s 3.833us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.060s 6.937us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.920s 6.766us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.960s 6.069us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 3.020s 191.164us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.470s 53.436us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.130s 15.305us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 16.580s 1482.148us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.130s 15.305us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.130s 15.305us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 16.580s 1482.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 1.070s 6.252us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.470s 10.002us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 60680950218358253182630317005952751992652383365441338491518668068407969258921 81
UVM_INFO @ 3833068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 47721398336251635014481404317831504027166572790201313453090340827197351059757 83
UVM_INFO @ 2384317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 75365042137610200263521434680879404113006439189459829644108882159906793210072 88
UVM_INFO @ 113818704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 33164399320169110215748951159270187009883157193267617137613610651195604348483 82
UVM_INFO @ 6766122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 29078717469203416987716919062618765343109837937703662840410770197202706527755 86
UVM_INFO @ 10001546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 91364696500531102883080829417830871194236561367985145623548945011177056960577 84
UVM_INFO @ 6069401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 2007305594811181087455775947848827499019676912518254728037200182539369282144 83
UVM_INFO @ 464940390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 51234420738593550931908277676015204931255151648815203782369355275094910618404 80
UVM_INFO @ 6251992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_tl_intg_err 22303201230374255201988669720626142034506767940144402802564111687736174003914 89
UVM_INFO @ 6937163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 24453829791504495915577466735177150658811541104262123164852030783959143662321 81
UVM_INFO @ 409927638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 16441209821196598390918365642702221043222378579517766420877951405743190923791 82
UVM_INFO @ 22023031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---