Simulation Results: csrng

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.75 %
  • code
  • 92.18 %
  • assert
  • 94.32 %
  • func
  • 73.74 %
  • block
  • 96.82 %
  • line
  • 97.55 %
  • branch
  • 92.09 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 25.128us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 19.138us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 5.000s 180.801us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 29.000s 833.128us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 50.468us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 75.736us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 5.000s 180.801us 1 1 100.00
csrng_csr_aliasing 2.000s 50.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
alerts 1 1 100.00
csrng_alert 18.000s 606.609us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 7.000s 160.654us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 7.000s 160.654us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 547.000s 31178.663us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 32.853us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 70.597us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 49.033us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 49.033us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 19.138us 1 1 100.00
csrng_csr_rw 5.000s 180.801us 1 1 100.00
csrng_csr_aliasing 2.000s 50.468us 1 1 100.00
csrng_same_csr_outstanding 4.000s 81.172us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 19.138us 1 1 100.00
csrng_csr_rw 5.000s 180.801us 1 1 100.00
csrng_csr_aliasing 2.000s 50.468us 1 1 100.00
csrng_same_csr_outstanding 4.000s 81.172us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 39.781us 1 1 100.00
csrng_tl_intg_err 5.000s 95.881us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 13.953us 1 1 100.00
csrng_csr_rw 5.000s 180.801us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 18.000s 606.609us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 547.000s 31178.663us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
csrng_sec_cm 2.000s 39.781us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
csrng_sec_cm 2.000s 39.781us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
csrng_sec_cm 2.000s 39.781us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
csrng_sec_cm 2.000s 39.781us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
csrng_sec_cm 2.000s 39.781us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 18.000s 606.609us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 547.000s 31178.663us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 18.000s 606.609us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 95.881us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
csrng_sec_cm 2.000s 39.781us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
csrng_sec_cm 2.000s 39.781us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 44.973us 1 1 100.00
csrng_err 2.000s 22.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 188.000s 8174.016us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 1 test run
csrng_stress_all_with_rand_reset 36274108527390905713908364212382979738662423137472146760132438678852616503372 232
UVM_INFO @ 8174015742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---