Simulation Results: dma

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.23 %
  • code
  • 90.73 %
  • assert
  • 96.50 %
  • func
  • 59.45 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 7.000s 415.236us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 8.000s 309.699us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 7.000s 683.940us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 38.994us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 53.674us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 17.000s 3772.773us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 89.591us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 24.837us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 53.674us 1 1 100.00
dma_csr_aliasing 3.000s 89.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 47.000s 32936.043us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 333.000s 39789.236us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 217.000s 48508.801us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 217.000s 48508.801us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 333.000s 39789.236us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 695.000s 57069.220us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 217.000s 48508.801us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 5.000s 313.183us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 312.000s 42583.640us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 86.621us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 25.434us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 5.000s 339.986us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 5.000s 339.986us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 38.994us 1 1 100.00
dma_csr_rw 1.000s 53.674us 1 1 100.00
dma_csr_aliasing 3.000s 89.591us 1 1 100.00
dma_same_csr_outstanding 3.000s 119.499us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 38.994us 1 1 100.00
dma_csr_rw 1.000s 53.674us 1 1 100.00
dma_csr_aliasing 3.000s 89.591us 1 1 100.00
dma_same_csr_outstanding 3.000s 119.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 19.000s 67.398us 1 1 100.00
dma_generic_stress 695.000s 57069.220us 1 1 100.00
dma_handshake_stress 217.000s 48508.801us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 367.982us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 242.135us 1 1 100.00
dma_sec_cm 1.000s 10.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 75.000s 12976.368us 1 1 100.00
dma_longer_transfer 12.000s 3010.583us 1 1 100.00
dma_stress_all_with_rand_reset 15.000s 1489.333us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 40166426254851034306685414305344314609211139927987877023241051067820027051788 127
UVM_INFO @ 1489332864ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---