Simulation Results: edn/edn0

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 80.81 %
  • code
  • 93.20 %
  • assert
  • 98.89 %
  • func
  • 50.35 %
  • block
  • 96.34 %
  • line
  • 98.20 %
  • branch
  • 91.88 %
  • toggle
  • 87.37 %
  • FSM
  • 95.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 40.873us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 35.678us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 17.770us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 175.514us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 31.860us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 3.000s 33.471us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 17.770us 1 1 100.00
edn_csr_aliasing 2.000s 31.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 114.867us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 114.867us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 114.867us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 28.233us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 81.675us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 39.431us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 13.198us 1 1 100.00
edn_disable_auto_req_mode 2.000s 110.450us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 11.000s 1490.774us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 32.417us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 24.141us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 5.000s 1573.865us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 5.000s 1573.865us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 35.678us 1 1 100.00
edn_csr_rw 2.000s 17.770us 1 1 100.00
edn_csr_aliasing 2.000s 31.860us 1 1 100.00
edn_same_csr_outstanding 2.000s 29.196us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 35.678us 1 1 100.00
edn_csr_rw 2.000s 17.770us 1 1 100.00
edn_csr_aliasing 2.000s 31.860us 1 1 100.00
edn_same_csr_outstanding 2.000s 29.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.000s 1529.175us 1 1 100.00
edn_tl_intg_err 3.000s 377.322us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 97.300us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 81.675us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.000s 1529.175us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.000s 1529.175us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.000s 1529.175us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.000s 1529.175us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 81.675us 1 1 100.00
edn_sec_cm 10.000s 1529.175us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 81.675us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 377.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 96.000s 16051.964us 1 1 100.00