Simulation Results: edn/edn1

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.27 %
  • code
  • 81.85 %
  • assert
  • 98.18 %
  • func
  • 78.78 %
  • line
  • 97.88 %
  • branch
  • 92.64 %
  • cond
  • 89.38 %
  • toggle
  • 87.29 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.140s 75.658us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.190s 34.291us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.080s 42.883us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.100s 85.735us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.070s 15.315us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.410s 21.977us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.080s 42.883us 1 1 100.00
edn_csr_aliasing 1.070s 15.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.600s 205.312us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.600s 205.312us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.600s 205.312us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.340s 23.914us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.400s 79.218us 1 1 100.00
errs 1 1 100.00
edn_err 1.480s 27.394us 1 1 100.00
disable 2 2 100.00
edn_disable 1.190s 11.108us 1 1 100.00
edn_disable_auto_req_mode 1.350s 47.198us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.600s 90.709us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.210s 59.798us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.210s 16.351us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.930s 170.904us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.930s 170.904us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.190s 34.291us 1 1 100.00
edn_csr_rw 1.080s 42.883us 1 1 100.00
edn_csr_aliasing 1.070s 15.315us 1 1 100.00
edn_same_csr_outstanding 1.310s 44.750us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.190s 34.291us 1 1 100.00
edn_csr_rw 1.080s 42.883us 1 1 100.00
edn_csr_aliasing 1.070s 15.315us 1 1 100.00
edn_same_csr_outstanding 1.310s 44.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.280s 533.563us 1 1 100.00
edn_tl_intg_err 2.730s 92.920us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.180s 69.453us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.400s 79.218us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.280s 533.563us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.280s 533.563us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.280s 533.563us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.280s 533.563us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.400s 79.218us 1 1 100.00
edn_sec_cm 4.280s 533.563us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.400s 79.218us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.730s 92.920us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 81.390s 6836.838us 1 1 100.00