Simulation Results: entropy_src/rng_16bits

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 70.32 %
  • code
  • 83.30 %
  • assert
  • 74.20 %
  • func
  • 53.47 %
  • block
  • 94.24 %
  • line
  • 97.88 %
  • branch
  • 86.36 %
  • toggle
  • 53.11 %
  • FSM
  • 95.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 83.880us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 107.470us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 56.045us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 19.000s 793.778us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 58.471us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 142.604us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 56.045us 1 1 100.00
entropy_src_csr_aliasing 2.000s 58.471us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 83.880us 1 1 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
entropy_src_fw_ov 506.000s 14097.042us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 506.000s 14097.042us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 683.000s 13039.179us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
entropy_src_intr 31.000s 5001.195us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
entropy_src_functional_alerts 8.000s 318.871us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 450.000s 13134.983us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 40.270us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 56.000s 1229.338us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 33.736us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 3.000s 18.241us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 107.290us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 107.290us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 107.470us 1 1 100.00
entropy_src_csr_rw 2.000s 56.045us 1 1 100.00
entropy_src_csr_aliasing 2.000s 58.471us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 46.857us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 107.470us 1 1 100.00
entropy_src_csr_rw 2.000s 56.045us 1 1 100.00
entropy_src_csr_aliasing 2.000s 58.471us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 46.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 4.000s 98.852us 1 1 100.00
entropy_src_tl_intg_err 7.000s 681.320us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
entropy_src_cfg_regwen 2.000s 22.921us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
entropy_src_fw_ov 506.000s 14097.042us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 40.270us 1 1 100.00
entropy_src_sec_cm 4.000s 98.852us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 40.270us 1 1 100.00
entropy_src_sec_cm 4.000s 98.852us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 529.000s 14024.772us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 40.270us 1 1 100.00
entropy_src_sec_cm 4.000s 98.852us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 40.270us 1 1 100.00
entropy_src_sec_cm 4.000s 98.852us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 40.270us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 8.000s 318.871us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 7.000s 681.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 137.000s 14328.422us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 20.000s 723.187us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 20078670302583339056034078614153027661431521581868553722143535445728503988138 635
UVM_INFO @ 723187417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---