Simulation Results: hmac

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.80 %
  • code
  • 83.15 %
  • assert
  • 96.96 %
  • func
  • 29.28 %
  • block
  • 97.42 %
  • line
  • 98.35 %
  • branch
  • 93.52 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.000s 441.364us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 19.698us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 29.280us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.000s 310.605us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 57.140us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 26.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 29.280us 1 1 100.00
hmac_csr_aliasing 3.000s 57.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 80.000s 1845.064us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 119.000s 2717.985us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 16.000s 1549.544us 1 1 100.00
hmac_test_sha384_vectors 583.000s 17462.060us 1 1 100.00
hmac_test_sha512_vectors 34.000s 1906.478us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 453.307us 1 1 100.00
hmac_test_hmac384_vectors 21.000s 955.746us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 354.015us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.000s 835.888us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 94.000s 3236.163us 1 1 100.00
error 1 1 100.00
hmac_error 19.000s 4991.594us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 100.000s 9482.366us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.000s 441.364us 1 1 100.00
hmac_long_msg 80.000s 1845.064us 1 1 100.00
hmac_back_pressure 119.000s 2717.985us 1 1 100.00
hmac_datapath_stress 94.000s 3236.163us 1 1 100.00
hmac_burst_wr 15.000s 835.888us 1 1 100.00
hmac_stress_all 486.000s 42856.591us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.000s 441.364us 1 1 100.00
hmac_long_msg 80.000s 1845.064us 1 1 100.00
hmac_back_pressure 119.000s 2717.985us 1 1 100.00
hmac_datapath_stress 94.000s 3236.163us 1 1 100.00
hmac_wipe_secret 100.000s 9482.366us 1 1 100.00
hmac_test_sha256_vectors 16.000s 1549.544us 1 1 100.00
hmac_test_sha384_vectors 583.000s 17462.060us 1 1 100.00
hmac_test_sha512_vectors 34.000s 1906.478us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 453.307us 1 1 100.00
hmac_test_hmac384_vectors 21.000s 955.746us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 354.015us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.000s 441.364us 1 1 100.00
hmac_long_msg 80.000s 1845.064us 1 1 100.00
hmac_back_pressure 119.000s 2717.985us 1 1 100.00
hmac_datapath_stress 94.000s 3236.163us 1 1 100.00
hmac_burst_wr 15.000s 835.888us 1 1 100.00
hmac_error 19.000s 4991.594us 1 1 100.00
hmac_wipe_secret 100.000s 9482.366us 1 1 100.00
hmac_test_sha256_vectors 16.000s 1549.544us 1 1 100.00
hmac_test_sha384_vectors 583.000s 17462.060us 1 1 100.00
hmac_test_sha512_vectors 34.000s 1906.478us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 453.307us 1 1 100.00
hmac_test_hmac384_vectors 21.000s 955.746us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 354.015us 1 1 100.00
hmac_stress_all 486.000s 42856.591us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 486.000s 42856.591us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 46.646us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 20.740us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 155.874us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 155.874us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 19.698us 1 1 100.00
hmac_csr_rw 1.000s 29.280us 1 1 100.00
hmac_csr_aliasing 3.000s 57.140us 1 1 100.00
hmac_same_csr_outstanding 2.000s 78.563us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 19.698us 1 1 100.00
hmac_csr_rw 1.000s 29.280us 1 1 100.00
hmac_csr_aliasing 3.000s 57.140us 1 1 100.00
hmac_same_csr_outstanding 2.000s 78.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 67.258us 1 1 100.00
hmac_tl_intg_err 4.000s 258.621us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 258.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.000s 441.364us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 6.000s 474.327us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 167.000s 9301.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 327.019us 1 1 100.00