Simulation Results: i2c

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.03 %
  • code
  • 85.62 %
  • assert
  • 97.25 %
  • func
  • 81.22 %
  • block
  • 95.92 %
  • line
  • 95.26 %
  • branch
  • 92.68 %
  • toggle
  • 72.52 %
  • FSM
  • 82.01 %
Validation stages
V1
100.00%
V2
78.05%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 75.000s 32859.697us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 18.000s 1311.007us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 2.000s 16.760us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 2.000s 145.426us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 4.000s 4705.572us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 2.000s 29.832us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.000s 24.047us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 2.000s 145.426us 1 1 100.00
i2c_csr_aliasing 2.000s 29.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 2.000s 33.895us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 3601.000s 0.000us 0 1 0.00
host_maxperf 0 1 0.00
i2c_host_perf 3600.000s 0.000us 0 1 0.00
host_override 1 1 100.00
i2c_host_override 2.000s 27.106us 1 1 100.00
host_fifo_watermark 0 1 0.00
i2c_host_fifo_watermark 3601.000s 0.000us 0 1 0.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 1326.000s 3321.126us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 2.000s 349.334us 1 1 100.00
i2c_host_fifo_fmt_empty 33.000s 1217.423us 1 1 100.00
i2c_host_fifo_reset_rx 4.000s 543.256us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 3194.000s 3628.288us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 8.000s 1621.263us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 3.000s 98.397us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 5.000s 462.390us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 36.000s 23462.776us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.000s 516.851us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 25.000s 1944.671us 1 1 100.00
i2c_target_intr_smoke 5.000s 464.635us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 3.000s 777.485us 1 1 100.00
i2c_target_fifo_reset_tx 2.000s 467.778us 1 1 100.00
target_fifo_full 1 3 33.33
i2c_target_stress_wr 3600.000s 0.000us 0 1 0.00
i2c_target_stress_rd 25.000s 1944.671us 1 1 100.00
i2c_target_intr_stress_wr 3601.000s 0.000us 0 1 0.00
target_timeout 1 1 100.00
i2c_target_timeout 9.000s 8772.508us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1589.000s 3556.412us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 7.000s 3932.771us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 49.000s 10248.623us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 4.000s 1950.725us 1 1 100.00
i2c_target_fifo_watermarks_tx 2.000s 528.968us 1 1 100.00
host_mode_config_perf 1 2 50.00
i2c_host_perf 3600.000s 0.000us 0 1 0.00
i2c_host_perf_precise 5.000s 136.249us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 8.000s 1621.263us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 5.000s 408.732us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 5.000s 2090.031us 1 1 100.00
i2c_target_nack_acqfull_addr 5.000s 6609.992us 1 1 100.00
i2c_target_nack_txstretch 3.000s 153.705us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 15.000s 419.480us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 4.000s 1207.618us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 1.000s 43.976us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 1.000s 31.487us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 3.000s 137.538us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 3.000s 137.538us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 2.000s 16.760us 1 1 100.00
i2c_csr_rw 2.000s 145.426us 1 1 100.00
i2c_csr_aliasing 2.000s 29.832us 1 1 100.00
i2c_same_csr_outstanding 1.000s 118.837us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 2.000s 16.760us 1 1 100.00
i2c_csr_rw 2.000s 145.426us 1 1 100.00
i2c_csr_aliasing 2.000s 29.832us 1 1 100.00
i2c_same_csr_outstanding 1.000s 118.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 3.000s 259.202us 1 1 100.00
i2c_sec_cm 2.000s 214.591us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 3.000s 259.202us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 5.000s 197.760us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 3.000s 812.806us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 11.000s 390.619us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 5 test runs
i2c_host_fifo_watermark 23632892919916889437978686761882738943965353844664632023665584391688461628349 None
i2c_host_perf 45322949863948059874092428303410003744812295266091240569377150490204576395553 None
i2c_host_stress_all 46982039792669249517382199645292315726168783938454182802520929042755784361251 None
i2c_target_stress_wr 56387379773158091196110196160596430213995535629261786989467689958004497908715 None
i2c_target_intr_stress_wr 76922849774651948550541269846636135654370431578943936559907093848188907096361 None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 1 test run
i2c_host_error_intr 80318052195693945298523367977082143931141001429331317997028648389870458099492 89
UVM_INFO @ 33895134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 79096236053701627097328241246969115623266450097498682412338523922858793798437 93
UVM_INFO @ 462390210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 9099543637000614113223911338436249207789132506805104773049744199078121534599 87
UVM_INFO @ 812806337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 111306841583462114032513426107052726708096559164186937582762706461491695977181 88
UVM_INFO @ 10248622582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 21732526078260877748830098458627827817867013982927111343638067096628283382422 93
UVM_INFO @ 197760431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1210) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
i2c_target_stress_all_with_rand_reset 113551036664707442386489627804307984133369347902815359459347369321657423620760 105
UVM_INFO @ 390619163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 1 test run
i2c_host_mode_toggle 64408410486583141601405070759391128255333834689681908126100447365017297033623 94
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17158