Simulation Results: lc_ctrl/volatile_unlock_disabled

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.68 %
  • code
  • 88.91 %
  • assert
  • 95.97 %
  • func
  • 75.16 %
  • block
  • 95.85 %
  • line
  • 96.66 %
  • branch
  • 89.43 %
  • toggle
  • 79.08 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 30.178us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 28.243us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 33.749us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 4.000s 100.627us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 15.393us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 95.585us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 33.749us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 15.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.000s 319.470us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 43.459us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 4.000s 180.803us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 4.000s 1481.521us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 3.000s 44.825us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 1241.081us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 532.580us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 245.593us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 1209.425us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 573.495us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 23.308us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 86.308us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 44.681us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 501.451us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 43.055us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.042s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 19.893us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 176.024us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 176.024us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 28.243us 1 1 100.00
lc_ctrl_csr_rw 1.000s 33.749us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 15.393us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 48.164us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 28.243us 1 1 100.00
lc_ctrl_csr_rw 1.000s 33.749us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 15.393us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 48.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 243.631us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 50.893us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 50.893us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.000s 319.470us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 243.631us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 243.631us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 243.631us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 243.631us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 243.631us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 243.631us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 243.631us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 243.631us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 180.803us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 355.868us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.000s 617.403us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.000s 617.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 6561416338973055657298582266946834273466386074411756127267184514674993313938 None
lc_ctrl_state_post_trans 46680072787837338728891858235118249563830074001510294276576905595279311716573 None
lc_ctrl_prog_failure 1204341242966108374609349547067392485920091862812683403005605715923467198309 None
lc_ctrl_errors 46200179028903967912001677237639446359010061783061773231557230808462491397031 None
lc_ctrl_jtag_state_failure 24284924832730589943385210945736096777655891979862103235015787215956368403146 None
lc_ctrl_jtag_state_post_trans 90678835266183931122782938920400676332070349747455128990104461199769907032270 None
lc_ctrl_jtag_prog_failure 109229815266064654240586331452303129315229295992700123141390789519563441176830 None
lc_ctrl_jtag_errors 109117424878479118624358373817365828586577931601648126686476536820498222872032 None
lc_ctrl_sec_mubi 47210454709846502419184696160386939850816632706277003783235092168625316964953 None
lc_ctrl_stress_all 51409316360593828254233481569391381256672774448107883027615994836431565184345 None
lc_ctrl_stress_all_with_rand_reset 85349703897334375011865238372950862394228593508313625812823699556571632028820 None