Simulation Results: lc_ctrl/volatile_unlock_enabled

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.62 %
  • code
  • 91.10 %
  • assert
  • 96.69 %
  • func
  • 78.06 %
  • block
  • 96.48 %
  • line
  • 97.27 %
  • branch
  • 91.08 %
  • toggle
  • 83.20 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 238.725us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 18.041us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 27.243us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 250.861us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 44.542us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 19.592us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 27.243us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 44.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 1506.905us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.154us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 1127.868us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 7.000s 1172.549us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 10.000s 835.130us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.000s 1176.839us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 67.827us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 51.041us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 2190.266us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 106.495us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 26.703us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 180.496us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 250.308us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 12.000s 1949.370us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 50.896us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.254s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 24.118us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 503.220us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 503.220us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 18.041us 1 1 100.00
lc_ctrl_csr_rw 2.000s 27.243us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 44.542us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 23.191us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 18.041us 1 1 100.00
lc_ctrl_csr_rw 2.000s 27.243us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 44.542us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 23.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 149.573us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 89.487us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 89.487us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 1506.905us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 149.573us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 149.573us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 149.573us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 149.573us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 149.573us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 149.573us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 149.573us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 149.573us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1127.868us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 326.519us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 1199.312us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 1199.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 85343373983776590613354887599004857557268586257433520051980440341764230488513 None
lc_ctrl_state_post_trans 108774384092845094338353623507582012738180428080214361948994562955713293009623 None
lc_ctrl_prog_failure 5506146211126103082271521858020009544620456146858658028886003107470788423208 None
lc_ctrl_errors 65053638569419035260005768368003516545806582403227417424354485966650745577899 None
lc_ctrl_jtag_state_failure 6221356872727247222026178039196640820786275041663042243704584881941559536451 None
lc_ctrl_jtag_state_post_trans 9775824926745736748675683466565675713261492930639418632370399698673428355215 None
lc_ctrl_jtag_prog_failure 14232546887150314230261679087972883136364329164712107837497831216456755899040 None
lc_ctrl_jtag_errors 82996892529752521926007071947076074866377239156817128372845068953007924238615 None
lc_ctrl_sec_mubi 13639705506820553388643124302403253631988634808669693680825690075916659421106 None
lc_ctrl_stress_all 86627954647714175213742846370427548210525332844057607070495479774533362463716 None
lc_ctrl_stress_all_with_rand_reset 14394328526774609508005130447652243890664811319478643843191038876845553756939 None