Simulation Results: otbn

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.41 %
  • code
  • 86.15 %
  • assert
  • 89.76 %
  • func
  • 98.31 %
  • block
  • 99.24 %
  • line
  • 99.45 %
  • branch
  • 94.55 %
  • toggle
  • 84.40 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
88.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 14.000s 401.114us 1 1 100.00
otbn_smoke_vectorized 11.000s 45.290us 1 1 100.00
single_binary 1 1 100.00
otbn_single 15.000s 303.406us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 37.943us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 16.430us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 11.000s 163.455us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 13.345us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 36.230us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 16.430us 1 1 100.00
otbn_csr_aliasing 5.000s 13.345us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 89.000s 2390.924us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 22.000s 745.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 42.000s 336.906us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 118.000s 302.584us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 36.000s 87.872us 0 1 0.00
stress_all 1 1 100.00
otbn_stress_all 91.000s 1299.109us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 11.000s 78.405us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 13.989us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 28.000s 66.554us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 35.393us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 39.601us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 199.790us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 199.790us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 37.943us 1 1 100.00
otbn_csr_rw 5.000s 16.430us 1 1 100.00
otbn_csr_aliasing 5.000s 13.345us 1 1 100.00
otbn_same_csr_outstanding 5.000s 23.568us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 37.943us 1 1 100.00
otbn_csr_rw 5.000s 16.430us 1 1 100.00
otbn_csr_aliasing 5.000s 13.345us 1 1 100.00
otbn_same_csr_outstanding 5.000s 23.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 68.329us 1 1 100.00
otbn_dmem_err 12.000s 58.356us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 12.000s 105.770us 1 1 100.00
otbn_controller_ispr_rdata_err 16.000s 31.146us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 51.992us 1 1 100.00
otbn_urnd_err 7.000s 10.240us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 24.466us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 9.000s 22.504us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 8.000s 23.809us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
otbn_tl_intg_err 28.000s 124.972us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 60.000s 352.974us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 14.000s 401.114us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 12.000s 58.356us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 68.329us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 28.000s 124.972us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 78.405us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 68.329us 1 1 100.00
otbn_dmem_err 12.000s 58.356us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 13.989us 1 1 100.00
otbn_illegal_mem_acc 8.000s 24.466us 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 15.000s 303.406us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 68.329us 1 1 100.00
otbn_dmem_err 12.000s 58.356us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 13.989us 1 1 100.00
otbn_illegal_mem_acc 8.000s 24.466us 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 78.405us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 68.329us 1 1 100.00
otbn_dmem_err 12.000s 58.356us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 13.989us 1 1 100.00
otbn_illegal_mem_acc 8.000s 24.466us 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 15.000s 303.406us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 13.000s 84.287us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 9.000s 18.216us 1 1 100.00
sec_cm_rnd_bus_consistency 0 1 0.00
otbn_rnd_sec_cm 49.000s 362.738us 0 1 0.00
sec_cm_rnd_rng_digest 0 1 0.00
otbn_rnd_sec_cm 49.000s 362.738us 0 1 0.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 11.000s 67.257us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 18.000s 297.800us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 8.000s 7.600us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 8.000s 7.600us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 7.000s 10.441us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 15.000s 303.406us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 15.000s 303.406us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 15.000s 303.406us 1 1 100.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 36.000s 87.872us 0 1 0.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 15.000s 303.406us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 15.000s 303.406us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 15.036us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 15.000s 303.406us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 249.000s 4997.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 138.000s 592.545us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 2 test runs
otbn_multi 82840522373800407019601365767909116412378760890867739261305241756552397633661 159
UVM_INFO @ 87872127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rnd_sec_cm 18351688427474853629408796757897386868312687276308011280133461788712028060242 125
UVM_INFO @ 362738078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 76304046675380184621181997719563665638314455624343291957034632792215022353551 119
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,158): (time 7599927 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 7599927 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 7599927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---