Simulation Results: otp_ctrl

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.85 %
  • code
  • 73.28 %
  • assert
  • 93.85 %
  • func
  • 60.43 %
  • line
  • 87.52 %
  • branch
  • 84.42 %
  • cond
  • 86.29 %
  • toggle
  • 69.65 %
  • FSM
  • 38.51 %
Validation stages
V1
100.00%
V2
75.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.430s 107.044us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 20.070s 3503.485us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.970s 381.758us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.580s 668.026us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.840s 310.620us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.840s 182.221us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.070s 131.453us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.580s 668.026us 1 1 100.00
otp_ctrl_csr_aliasing 3.840s 182.221us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.300s 81.999us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.970s 45.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 353.680s 113062.808us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.060s 164.287us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 39.510s 1249.397us 1 1 100.00
otp_ctrl_check_fail 19.550s 1072.092us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.040s 273.037us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 16.720s 1549.317us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 10.470s 402.687us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 22.170s 1670.097us 1 1 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 57.530s 2531.347us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 24.400s 2179.182us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 3.980s 186.157us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 12.660s 383.214us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.810s 61.975us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.030s 56.793us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.770s 76.773us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.770s 76.773us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.970s 381.758us 1 1 100.00
otp_ctrl_csr_rw 2.580s 668.026us 1 1 100.00
otp_ctrl_csr_aliasing 3.840s 182.221us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.110s 742.431us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.970s 381.758us 1 1 100.00
otp_ctrl_csr_rw 2.580s 668.026us 1 1 100.00
otp_ctrl_csr_aliasing 3.840s 182.221us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.110s 742.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
otp_ctrl_tl_intg_err 28.860s 12190.459us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 28.860s 12190.459us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 20.070s 3503.485us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 20.070s 3503.485us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
otp_ctrl_macro_errs 24.400s 2179.182us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
otp_ctrl_macro_errs 24.400s 2179.182us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.140s 2372.471us 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.060s 164.287us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 19.550s 1072.092us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 16.720s 1549.317us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 16.720s 1549.317us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 16.720s 1549.317us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 16.720s 1549.317us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 16.720s 1549.317us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 20.070s 3503.485us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 16.720s 1549.317us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 20.070s 3503.485us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 449.590s 78296.134us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.040s 273.037us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 20.070s 3503.485us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 20.070s 3503.485us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 24.400s 2179.182us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 122.930s 62948.993us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 112.010s 9721.017us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_test_access 58440664145440578454497601887497911659286636795871163807873747154161213405790 2694
UVM_INFO @ 186156863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 100505074318036943563858311258977520860558449912061326523424713210018861384294 6427
UVM_INFO @ 383214130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 76876129307001924733881222613415386271217938085901594034479474505619849214138 113005
UVM_INFO @ 113062807552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 85627072787034498051791645089013366964871443420750812832448178219064709589609 95
UVM_INFO @ 62948993383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_dai_lock 51906870211487248590671161703822821735014180146509600055740079499492099490671 11681
UVM_INFO @ 1549316600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 113209250362022024100674536186656100125364117776863079391830980959386876788002 6639
UVM_INFO @ 2179181613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 18151352934826622670873724277830388332661836505179964752668486609821342186001 64262
UVM_INFO @ 9721016516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---