Simulation Results: rom_ctrl/32kb

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.30 %
  • code
  • 79.78 %
  • assert
  • 97.53 %
  • func
  • 93.59 %
  • block
  • 78.57 %
  • line
  • 79.01 %
  • branch
  • 79.53 %
  • toggle
  • 84.40 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 250.887us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 60.378us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 61.196us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 82.387us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 75.080us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 70.569us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 61.196us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 75.080us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 57.197us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 63.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 26.689us 0 1 0.00
stress_all 0 1 0.00
rom_ctrl_stress_all 10800.000s 0.000us 0 1 0.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 2.000s 64.855us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 50.185us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 85.464us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 85.464us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 60.378us 1 1 100.00
rom_ctrl_csr_rw 3.000s 61.196us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 75.080us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 74.622us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 60.378us 1 1 100.00
rom_ctrl_csr_rw 3.000s 61.196us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 75.080us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 74.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.000s 1071.296us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 70.000s 303.228us 1 1 100.00
rom_ctrl_tl_intg_err 24.000s 3790.137us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 70.000s 303.228us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 70.000s 303.228us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 70.000s 303.228us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 70.000s 303.228us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 250.887us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 250.887us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 250.887us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.000s 3790.137us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 2.000s 64.855us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.000s 1071.296us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 70.000s 303.228us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 16.000s 1089.326us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
rom_ctrl_stress_all 92758126165008930691505998405275598155478366205528872035681139416118167195613 None
rom_ctrl_corrupt_sig_fatal_chk 107187103533280859872686508886871409944467889407438853777288773027318528734898 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 67015044548875804480952039099553918413106490350651980021799833590359311290310 88
UVM_INFO @ 26689116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---