Simulation Results: rom_ctrl/64kb

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.12 %
  • code
  • 78.59 %
  • assert
  • 97.38 %
  • func
  • 97.39 %
  • block
  • 78.48 %
  • line
  • 78.92 %
  • branch
  • 79.30 %
  • toggle
  • 84.69 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
66.67%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 1486.582us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 101.457us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 80.649us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 63.630us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 77.646us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 75.083us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 80.649us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 77.646us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 69.126us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 129.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 5.000s 416.209us 0 1 0.00
stress_all 0 1 0.00
rom_ctrl_stress_all 10800.000s 0.000us 0 1 0.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 53.620us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 558.741us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 558.741us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 101.457us 1 1 100.00
rom_ctrl_csr_rw 3.000s 80.649us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 77.646us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 76.033us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.000s 101.457us 1 1 100.00
rom_ctrl_csr_rw 3.000s 80.649us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 77.646us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 76.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.000s 277.971us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 250.000s 890.542us 1 1 100.00
rom_ctrl_tl_intg_err 56.000s 284.314us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 250.000s 890.542us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 250.000s 890.542us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 250.000s 890.542us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 250.000s 890.542us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 1486.582us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 1486.582us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 1486.582us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 56.000s 284.314us 1 1 100.00
sec_cm_bus_local_esc 0 2 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.000s 277.971us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 250.000s 890.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 16.000s 5280.326us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
rom_ctrl_stress_all 75738225621566823845766560371211414880656869945509182143259374377304785572399 None
rom_ctrl_corrupt_sig_fatal_chk 34367272053850523088043621746726011246497884809236329363145566769603091498444 None
rom_ctrl_kmac_err_chk 39985776744048853553540124271113727922602197061826655785235294523885943182321 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 89531159366801984502628342556136250539439144088300194061548640071692233575480 88
UVM_INFO @ 416209325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---