Simulation Results: rstmgr

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.08 %
  • code
  • 99.22 %
  • assert
  • 98.35 %
  • func
  • 93.67 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.64 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.600s 76.091us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.710s 91.003us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.240s 36.579us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.950s 57.961us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.360s 38.984us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.590s 66.921us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.240s 36.579us 1 1 100.00
rstmgr_csr_aliasing 1.360s 38.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.570s 88.337us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.480s 39.018us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.800s 96.708us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.880s 461.180us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.880s 461.180us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.880s 461.180us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.880s 461.180us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 5.440s 637.884us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.290s 40.659us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.420s 59.816us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.420s 59.816us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.710s 91.003us 1 1 100.00
rstmgr_csr_rw 1.240s 36.579us 1 1 100.00
rstmgr_csr_aliasing 1.360s 38.984us 1 1 100.00
rstmgr_same_csr_outstanding 1.390s 37.908us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.710s 91.003us 1 1 100.00
rstmgr_csr_rw 1.240s 36.579us 1 1 100.00
rstmgr_csr_aliasing 1.360s 38.984us 1 1 100.00
rstmgr_same_csr_outstanding 1.390s 37.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 28.010s 3415.165us 1 1 100.00
rstmgr_tl_intg_err 4.180s 344.009us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 28.010s 3415.165us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 28.010s 3415.165us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.180s 344.009us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.490s 61.241us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.830s 423.562us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.500s 291.120us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 28.010s 3415.165us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.240s 36.579us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.240s 36.579us 1 1 100.00