Simulation Results: rv_timer

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 90.39 %
  • assert
  • 96.52 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 72.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 153.783us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 2.000s 15.735us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 12.283us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 381.991us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 26.909us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 18.021us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 12.283us 1 1 100.00
rv_timer_csr_aliasing 1.000s 26.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 68.301us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 94.736us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 559.000s 1205986.569us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 559.000s 1205986.569us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 10.000s 2402.611us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 2.000s 15.980us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 24.851us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 43.272us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 43.272us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 15.735us 1 1 100.00
rv_timer_csr_rw 1.000s 12.283us 1 1 100.00
rv_timer_csr_aliasing 1.000s 26.909us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 37.332us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 15.735us 1 1 100.00
rv_timer_csr_rw 1.000s 12.283us 1 1 100.00
rv_timer_csr_aliasing 1.000s 26.909us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 37.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 35.817us 1 1 100.00
rv_timer_tl_intg_err 2.000s 152.636us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 152.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 319.027us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 228.028us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 34.000s 4564.874us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 25923414236866952202182996800171602580707908898040501304682132676337986945256 84
UVM_INFO @ 319026557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 52405441346865518383496782209474584196327259652085918387514777415714299213172 84
UVM_INFO @ 228027689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---