Simulation Results: spi_host

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.49 %
  • code
  • 91.14 %
  • assert
  • 95.09 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 51.000s 1759.063us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 30.497us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 21.838us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 530.280us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 39.728us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 93.330us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 21.838us 1 1 100.00
spi_host_csr_aliasing 2.000s 39.728us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 21.891us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 23.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 264.887us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 14.000s 870.686us 1 1 100.00
spi_host_error_cmd 1.000s 94.813us 1 1 100.00
spi_host_event 25.000s 5883.162us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 82.475us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 82.475us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 82.475us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 193.000s 28002.043us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 356.000s 11804.409us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 78.705us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 82.475us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 82.475us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 51.000s 1759.063us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 51.000s 1759.063us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 7.000s 544.703us 1 1 100.00
spien 1 1 100.00
spi_host_spien 128.000s 87436.526us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 13.000s 1108.279us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 4.000s 155.244us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 14.000s 870.686us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 22.889us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 37.982us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 156.760us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 156.760us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.497us 1 1 100.00
spi_host_csr_rw 1.000s 21.838us 1 1 100.00
spi_host_csr_aliasing 2.000s 39.728us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 52.213us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.497us 1 1 100.00
spi_host_csr_rw 1.000s 21.838us 1 1 100.00
spi_host_csr_aliasing 2.000s 39.728us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 52.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 52.010us 1 1 100.00
spi_host_sec_cm 2.000s 133.750us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 52.010us 1 1 100.00