Simulation Results: sram_ctrl/main

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 94.64 %
  • code
  • 93.72 %
  • assert
  • 97.01 %
  • func
  • 93.20 %
  • block
  • 92.73 %
  • line
  • 93.64 %
  • branch
  • 89.45 %
  • toggle
  • 91.79 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 708.059us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 31.592us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.539us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 127.416us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.931us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 351.025us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 17.539us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.931us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 118.000s 5914.494us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 118.000s 5380.314us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 36.000s 6102.119us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 164.000s 7694.194us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 236.000s 30322.021us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 91.000s 127571.678us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 24.000s 20224.677us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 27.000s 55557.014us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 384.948us 1 1 100.00
sram_ctrl_partial_access_b2b 196.000s 5045.718us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 3175.741us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 704.262us 1 1 100.00
sram_ctrl_throughput_w_readback 6.000s 1408.171us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 21.000s 22978.024us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 344.476us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 6.000s 708.059us 1 1 100.00
sram_ctrl_partial_access 5.000s 384.948us 1 1 100.00
sram_ctrl_access_during_key_req 91.000s 127571.678us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 252.000s 14052.703us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 20.242us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 40.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 40.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 31.592us 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.539us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.931us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.621us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 31.592us 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.539us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.931us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 36.000s 26159.232us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 411.893us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 195.874us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 411.893us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 195.874us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 21.000s 22978.024us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 21.000s 22978.024us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.539us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 27.000s 55557.014us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 55557.014us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 55557.014us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 24.000s 20224.677us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 36.000s 26159.232us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 708.059us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 708.059us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 27.000s 55557.014us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 411.893us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 24.000s 20224.677us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 411.893us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 411.893us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 708.059us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 411.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 24.000s 1208.845us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 59492417445010375611241457062519834802999537279218237532803672547853475807157 None
sram_ctrl_mubi_enc_err 100066877957487715604093162835181902678725085744230178853404580564002474231692 None