Simulation Results: sram_ctrl/ret

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.61 %
  • code
  • 81.41 %
  • assert
  • 97.81 %
  • func
  • 92.60 %
  • block
  • 91.85 %
  • line
  • 93.41 %
  • branch
  • 87.60 %
  • toggle
  • 77.94 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 116.402us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.994us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 41.243us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 34.738us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 43.655us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 36.020us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 41.243us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 43.655us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 11.000s 1592.514us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 126.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 14.000s 411.428us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 201.000s 5794.455us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 572.879us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 663.858us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 651.277us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 10.000s 791.754us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 199.801us 1 1 100.00
sram_ctrl_partial_access_b2b 160.000s 6362.737us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 35.910us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 55.421us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 45.136us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 2268.546us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 87.437us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 116.402us 1 1 100.00
sram_ctrl_partial_access 2.000s 199.801us 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 663.858us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 39.000s 1934.370us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 29.702us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 295.854us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 295.854us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.994us 1 1 100.00
sram_ctrl_csr_rw 2.000s 41.243us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 43.655us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 89.353us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.994us 1 1 100.00
sram_ctrl_csr_rw 2.000s 41.243us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 43.655us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 89.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 392.456us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 601.916us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 378.054us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 601.916us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 378.054us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 2268.546us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 2268.546us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 41.243us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 10.000s 791.754us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 791.754us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 791.754us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 651.277us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 392.456us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 116.402us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 116.402us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 10.000s 791.754us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 601.916us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 651.277us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 601.916us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 601.916us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 116.402us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 601.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 86.000s 2035.304us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 112029125196394782806715715759627929366567398217767437495627731823826670804873 None
sram_ctrl_mubi_enc_err 35727918617329001839049849775679587791144114359761922046195962169841120898522 None