Simulation Results: uart

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 93.52 %
  • code
  • 92.73 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 293.878us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 35.841us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 20.432us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 168.083us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 45.411us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 369.354us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 20.432us 1 1 100.00
uart_csr_aliasing 2.000s 45.411us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 111.000s 123392.446us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 293.878us 1 1 100.00
uart_tx_rx 111.000s 123392.446us 1 1 100.00
parity_error 2 2 100.00
uart_intr 61.000s 27729.136us 1 1 100.00
uart_rx_parity_err 52.000s 70612.557us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 111.000s 123392.446us 1 1 100.00
uart_intr 61.000s 27729.136us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 16.000s 35605.659us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 33.000s 33993.418us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 46.000s 24126.828us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 61.000s 27729.136us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 61.000s 27729.136us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 61.000s 27729.136us 1 1 100.00
perf 1 1 100.00
uart_perf 242.000s 9654.482us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.000s 134.451us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.000s 134.451us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 24.000s 25374.943us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 89.000s 54762.307us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 5.000s 1463.495us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.000s 1929.975us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 566.000s 73528.787us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 20.000s 30736.186us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 1.000s 41.048us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 105.934us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 77.736us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 77.736us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 35.841us 1 1 100.00
uart_csr_rw 1.000s 20.432us 1 1 100.00
uart_csr_aliasing 2.000s 45.411us 1 1 100.00
uart_same_csr_outstanding 1.000s 88.544us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 35.841us 1 1 100.00
uart_csr_rw 1.000s 20.432us 1 1 100.00
uart_csr_aliasing 2.000s 45.411us 1 1 100.00
uart_same_csr_outstanding 1.000s 88.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 42.393us 1 1 100.00
uart_tl_intg_err 1.000s 76.635us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 76.635us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 43.000s 3424.226us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 14353044813243034681931032186610644901069729990425967992441479367492303716081 84
UVM_ERROR @ 24633989901 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 24634010309 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 24634051125 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 24634071533 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_stress_all 46268430891898240271097382144224626712200247137364157587934509448477059044056 94
UVM_ERROR @ 30495371110 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 30693074616 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 30702407940 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 30714407928 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0