Simulation Results: aes/gcm_unmasked

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.89 %
  • code
  • 90.68 %
  • assert
  • 97.94 %
  • func
  • 66.05 %
  • block
  • 89.93 %
  • line
  • 91.81 %
  • branch
  • 82.14 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
88.24%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 114.644us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 150.806us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 67.411us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 61.224us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 1456.396us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 61.520us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 110.004us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 61.224us 1 1 100.00
aes_csr_aliasing 1.000s 61.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 150.806us 1 1 100.00
aes_config_error 3.000s 229.063us 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 150.806us 1 1 100.00
aes_config_error 3.000s 229.063us 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 76.411us 1 1 100.00
aes_b2b 3.000s 180.501us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 150.806us 1 1 100.00
aes_config_error 3.000s 229.063us 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
aes_alert_reset 2434.000s 200000.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 70.522us 1 1 100.00
aes_config_error 3.000s 229.063us 1 1 100.00
aes_alert_reset 2434.000s 200000.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 173.483us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 1065.353us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 2434.000s 200000.000us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 76.411us 1 1 100.00
aes_sideload 2.000s 79.628us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 6.000s 225.032us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10801.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 83.422us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 213.700us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 213.700us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 67.411us 1 1 100.00
aes_csr_rw 2.000s 61.224us 1 1 100.00
aes_csr_aliasing 1.000s 61.520us 1 1 100.00
aes_same_csr_outstanding 2.000s 367.875us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 67.411us 1 1 100.00
aes_csr_rw 2.000s 61.224us 1 1 100.00
aes_csr_aliasing 1.000s 61.520us 1 1 100.00
aes_same_csr_outstanding 2.000s 367.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 130.623us 1 1 100.00
fault_inject 0 3 0.00
aes_fi 917.000s 200000.000us 0 1 0.00
aes_control_fi 20.000s 10011.622us 0 1 0.00
aes_cipher_fi 26.000s 10015.007us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 109.352us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 109.352us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 109.352us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 109.352us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 199.678us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 681.906us 1 1 100.00
aes_tl_intg_err 4.000s 231.350us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 231.350us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 2434.000s 200000.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 109.352us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 109.352us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 150.806us 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
aes_alert_reset 2434.000s 200000.000us 0 1 0.00
aes_core_fi 3.000s 125.923us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 229.063us 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
aes_core_fi 3.000s 125.923us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 109.352us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 86.378us 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 76.411us 1 1 100.00
aes_sideload 2.000s 79.628us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 86.378us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 86.378us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 86.378us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 86.378us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 86.378us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 76.411us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 917.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_redun 1 4 25.00
aes_fi 917.000s 200000.000us 0 1 0.00
aes_control_fi 20.000s 10011.622us 0 1 0.00
aes_cipher_fi 26.000s 10015.007us 0 1 0.00
aes_ctr_fi 3.000s 125.688us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 917.000s 200000.000us 0 1 0.00
sec_cm_cipher_fsm_redun 0 3 0.00
aes_fi 917.000s 200000.000us 0 1 0.00
aes_control_fi 20.000s 10011.622us 0 1 0.00
aes_cipher_fi 26.000s 10015.007us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 26.000s 10015.007us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 917.000s 200000.000us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 917.000s 200000.000us 0 1 0.00
aes_control_fi 20.000s 10011.622us 0 1 0.00
aes_ctr_fi 3.000s 125.688us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 917.000s 200000.000us 0 1 0.00
sec_cm_ctrl_sparse 1 4 25.00
aes_fi 917.000s 200000.000us 0 1 0.00
aes_control_fi 20.000s 10011.622us 0 1 0.00
aes_cipher_fi 26.000s 10015.007us 0 1 0.00
aes_ctr_fi 3.000s 125.688us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 2434.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_local_esc 1 4 25.00
aes_fi 917.000s 200000.000us 0 1 0.00
aes_control_fi 20.000s 10011.622us 0 1 0.00
aes_cipher_fi 26.000s 10015.007us 0 1 0.00
aes_ctr_fi 3.000s 125.688us 1 1 100.00
sec_cm_cipher_fsm_local_esc 1 4 25.00
aes_fi 917.000s 200000.000us 0 1 0.00
aes_control_fi 20.000s 10011.622us 0 1 0.00
aes_cipher_fi 26.000s 10015.007us 0 1 0.00
aes_ctr_fi 3.000s 125.688us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 917.000s 200000.000us 0 1 0.00
aes_control_fi 20.000s 10011.622us 0 1 0.00
aes_ctr_fi 3.000s 125.688us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 917.000s 200000.000us 0 1 0.00
sec_cm_data_reg_local_esc 0 3 0.00
aes_fi 917.000s 200000.000us 0 1 0.00
aes_control_fi 20.000s 10011.622us 0 1 0.00
aes_cipher_fi 26.000s 10015.007us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 604.483us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
aes_alert_reset 26949788889461450538841208699669617822713068705527439997258831921151516228945 3712702
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_fi 36750694336583278277331415511428461893132874373508600343176027033513984775674 1395366
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 113366540260107905698032582043291508211662402189136374757592311228007703646988 147
UVM_INFO @ 10011622169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:623) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 1 test run
aes_cipher_fi 11812331556333746603096209807361127134997462884458317037119437091718380052941 138
UVM_INFO @ 10015007036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_stress_all 9431894178537065976834754492688227931935949067299784373003572966358662768071 None
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 86364506915310102590256075564853805594453716678567141443649277798857740356445 420
UVM_INFO @ 604483085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---