Simulation Results: alert_handler

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.48 %
  • code
  • 90.98 %
  • assert
  • 98.29 %
  • func
  • 76.18 %
  • line
  • 99.75 %
  • branch
  • 97.81 %
  • cond
  • 90.69 %
  • toggle
  • 87.62 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 19.270s 1873.043us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 13.160s 256.826us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 10.250s 256.236us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 144.990s 1479.886us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 156.770s 3466.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.650s 885.330us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 10.250s 256.236us 1 1 100.00
alert_handler_csr_aliasing 156.770s 3466.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 332.710s 41059.087us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 34.930s 708.204us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1858.470s 48078.916us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 40.210s 1439.143us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 19.270s 1873.043us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 49.460s 881.732us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 26.280s 542.293us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 190.340s 14155.126us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 892.360s 11629.059us 1 1 100.00
alert_handler_lpg_stub_clk 1719.200s 120772.208us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2019.710s 19869.276us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 24.490s 717.148us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.520s 21.797us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.050s 11.356us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 30.460s 773.066us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 30.460s 773.066us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 13.160s 256.826us 1 1 100.00
alert_handler_csr_rw 10.250s 256.236us 1 1 100.00
alert_handler_csr_aliasing 156.770s 3466.091us 1 1 100.00
alert_handler_same_csr_outstanding 23.760s 197.487us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 13.160s 256.826us 1 1 100.00
alert_handler_csr_rw 10.250s 256.236us 1 1 100.00
alert_handler_csr_aliasing 156.770s 3466.091us 1 1 100.00
alert_handler_same_csr_outstanding 23.760s 197.487us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 206.960s 5172.070us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 206.960s 5172.070us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 206.960s 5172.070us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 206.960s 5172.070us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 361.750s 9782.525us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
alert_handler_tl_intg_err 4.990s 43.007us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 4.990s 43.007us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 206.960s 5172.070us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 19.270s 1873.043us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 19.270s 1873.043us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 19.270s 1873.043us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 19.270s 1873.043us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 40.210s 1439.143us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 892.360s 11629.059us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 40.210s 1439.143us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1858.470s 48078.916us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1858.470s 48078.916us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 13.120s 1009.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 167.240s 7708.823us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 5445449900358963331658652852553306326401474096630562676455435197535325536500 105
UVM_INFO @ 14155125645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 88275989832579925394935929415028412380952587399813535483292958391696930088459 228
UVM_INFO @ 717148318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 69863053741021783461334785207791073122940545324228134979646951754635977459331 131
UVM_INFO @ 7708822949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---