Simulation Results: dma

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.70 %
  • code
  • 90.03 %
  • assert
  • 96.61 %
  • func
  • 61.45 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 698.502us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 6.000s 310.107us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 1142.998us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 93.739us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 30.556us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 911.671us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 41.333us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 19.191us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 30.556us 1 1 100.00
dma_csr_aliasing 2.000s 41.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 84.000s 3937.693us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 586.000s 231772.846us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 1154.000s 71794.668us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 1154.000s 71794.668us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 586.000s 231772.846us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 674.000s 49992.204us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 1154.000s 71794.668us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 14.000s 2733.277us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 135.000s 30658.736us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 68.068us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 29.743us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 26.938us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 26.938us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 93.739us 1 1 100.00
dma_csr_rw 2.000s 30.556us 1 1 100.00
dma_csr_aliasing 2.000s 41.333us 1 1 100.00
dma_same_csr_outstanding 2.000s 38.983us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 93.739us 1 1 100.00
dma_csr_rw 2.000s 30.556us 1 1 100.00
dma_csr_aliasing 2.000s 41.333us 1 1 100.00
dma_same_csr_outstanding 2.000s 38.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 22.000s 191.930us 1 1 100.00
dma_generic_stress 674.000s 49992.204us 1 1 100.00
dma_handshake_stress 1154.000s 71794.668us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 1103.473us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 204.030us 1 1 100.00
dma_sec_cm 2.000s 10.799us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 123.000s 33448.329us 1 1 100.00
dma_longer_transfer 3.000s 163.171us 1 1 100.00
dma_stress_all_with_rand_reset 4.000s 332.686us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 19709183550088264500938324292755131313320150595539175975226245269759096807187 93
UVM_INFO @ 332686156ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---