Simulation Results: edn/edn0

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 78.47 %
  • code
  • 88.92 %
  • assert
  • 97.12 %
  • func
  • 49.37 %
  • block
  • 95.51 %
  • line
  • 97.81 %
  • branch
  • 90.23 %
  • toggle
  • 76.15 %
  • FSM
  • 91.47 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 16.554us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 27.276us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 92.174us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.000s 47.678us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 15.616us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 82.557us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 92.174us 1 1 100.00
edn_csr_aliasing 1.000s 15.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 68.721us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 68.721us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 68.721us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 26.229us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 137.428us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 37.268us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 18.229us 1 1 100.00
edn_disable_auto_req_mode 2.000s 91.420us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 12.000s 1045.439us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 13.075us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 18.463us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 27.461us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 27.461us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 27.276us 1 1 100.00
edn_csr_rw 2.000s 92.174us 1 1 100.00
edn_csr_aliasing 1.000s 15.616us 1 1 100.00
edn_same_csr_outstanding 2.000s 106.995us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 27.276us 1 1 100.00
edn_csr_rw 2.000s 92.174us 1 1 100.00
edn_csr_aliasing 1.000s 15.616us 1 1 100.00
edn_same_csr_outstanding 2.000s 106.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 11.000s 597.325us 1 1 100.00
edn_tl_intg_err 3.000s 66.309us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 18.727us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 137.428us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 11.000s 597.325us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 11.000s 597.325us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 11.000s 597.325us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 11.000s 597.325us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 137.428us 1 1 100.00
edn_sec_cm 11.000s 597.325us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 137.428us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 66.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 36.000s 4927.804us 1 1 100.00