Simulation Results: edn/edn1

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.34 %
  • code
  • 82.95 %
  • assert
  • 97.14 %
  • func
  • 81.93 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 89.92 %
  • toggle
  • 87.68 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.220s 29.852us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.100s 47.074us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.230s 26.258us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.600s 1976.619us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 44.718us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.940s 25.943us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.230s 26.258us 1 1 100.00
edn_csr_aliasing 1.030s 44.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.010s 53.197us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.010s 53.197us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.010s 53.197us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.290s 29.152us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.470s 28.137us 1 1 100.00
errs 1 1 100.00
edn_err 1.440s 38.588us 1 1 100.00
disable 2 2 100.00
edn_disable 1.190s 15.072us 1 1 100.00
edn_disable_auto_req_mode 1.100s 22.695us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.240s 95.562us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.170s 24.937us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.110s 52.370us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.870s 138.278us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.870s 138.278us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.100s 47.074us 1 1 100.00
edn_csr_rw 1.230s 26.258us 1 1 100.00
edn_csr_aliasing 1.030s 44.718us 1 1 100.00
edn_same_csr_outstanding 1.350s 77.357us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.100s 47.074us 1 1 100.00
edn_csr_rw 1.230s 26.258us 1 1 100.00
edn_csr_aliasing 1.030s 44.718us 1 1 100.00
edn_same_csr_outstanding 1.350s 77.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.420s 2211.781us 1 1 100.00
edn_tl_intg_err 2.730s 784.835us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.330s 20.016us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.470s 28.137us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.420s 2211.781us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.420s 2211.781us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.420s 2211.781us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.420s 2211.781us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.470s 28.137us 1 1 100.00
edn_sec_cm 5.420s 2211.781us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.470s 28.137us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.730s 784.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 69.300s 9964.400us 1 1 100.00