Simulation Results: entropy_src/rng_16bits

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 68.99 %
  • code
  • 82.56 %
  • assert
  • 72.94 %
  • func
  • 51.47 %
  • block
  • 94.10 %
  • line
  • 97.79 %
  • branch
  • 86.07 %
  • toggle
  • 52.64 %
  • FSM
  • 93.75 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 20.021us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 3.000s 44.059us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 51.749us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 14.000s 1670.351us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 28.357us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 195.572us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 51.749us 1 1 100.00
entropy_src_csr_aliasing 3.000s 28.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 20.021us 1 1 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
entropy_src_fw_ov 139.000s 13059.988us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 139.000s 13059.988us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 204.000s 14194.614us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
entropy_src_intr 30.000s 1591.500us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
entropy_src_functional_alerts 8.000s 1228.619us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 410.000s 13107.050us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 44.654us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 52.770us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 33.940us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 65.386us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 6.000s 156.800us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 6.000s 156.800us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 44.059us 1 1 100.00
entropy_src_csr_rw 2.000s 51.749us 1 1 100.00
entropy_src_csr_aliasing 3.000s 28.357us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 151.976us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 44.059us 1 1 100.00
entropy_src_csr_rw 2.000s 51.749us 1 1 100.00
entropy_src_csr_aliasing 3.000s 28.357us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 151.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 4.000s 107.733us 1 1 100.00
entropy_src_tl_intg_err 3.000s 264.655us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
entropy_src_cfg_regwen 2.000s 14.843us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
entropy_src_fw_ov 139.000s 13059.988us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 44.654us 1 1 100.00
entropy_src_sec_cm 4.000s 107.733us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 44.654us 1 1 100.00
entropy_src_sec_cm 4.000s 107.733us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 76.000s 14162.550us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 44.654us 1 1 100.00
entropy_src_sec_cm 4.000s 107.733us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 44.654us 1 1 100.00
entropy_src_sec_cm 4.000s 107.733us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 44.654us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 8.000s 1228.619us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 264.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 465.000s 13079.087us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 4.000s 314.095us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 58031384947596891360271684395276250744750590139288562753023891709979537546950 123
UVM_INFO @ 314094675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---