Simulation Results: hmac

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.86 %
  • code
  • 83.19 %
  • assert
  • 97.17 %
  • func
  • 29.21 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 15.000s 1074.886us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 20.661us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 24.127us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.000s 1330.099us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 58.768us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 20.900us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 24.127us 1 1 100.00
hmac_csr_aliasing 2.000s 58.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 29.000s 2509.924us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 68.000s 1573.908us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 322.000s 29139.998us 1 1 100.00
hmac_test_sha384_vectors 478.000s 14369.800us 1 1 100.00
hmac_test_sha512_vectors 633.000s 72395.056us 1 1 100.00
hmac_test_hmac256_vectors 20.000s 1731.712us 1 1 100.00
hmac_test_hmac384_vectors 16.000s 1457.004us 1 1 100.00
hmac_test_hmac512_vectors 25.000s 2126.793us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 31.000s 2176.014us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 62.000s 1362.377us 1 1 100.00
error 1 1 100.00
hmac_error 116.000s 4298.819us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 107.000s 9596.726us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 15.000s 1074.886us 1 1 100.00
hmac_long_msg 29.000s 2509.924us 1 1 100.00
hmac_back_pressure 68.000s 1573.908us 1 1 100.00
hmac_datapath_stress 62.000s 1362.377us 1 1 100.00
hmac_burst_wr 31.000s 2176.014us 1 1 100.00
hmac_stress_all 221.000s 16027.854us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 15.000s 1074.886us 1 1 100.00
hmac_long_msg 29.000s 2509.924us 1 1 100.00
hmac_back_pressure 68.000s 1573.908us 1 1 100.00
hmac_datapath_stress 62.000s 1362.377us 1 1 100.00
hmac_wipe_secret 107.000s 9596.726us 1 1 100.00
hmac_test_sha256_vectors 322.000s 29139.998us 1 1 100.00
hmac_test_sha384_vectors 478.000s 14369.800us 1 1 100.00
hmac_test_sha512_vectors 633.000s 72395.056us 1 1 100.00
hmac_test_hmac256_vectors 20.000s 1731.712us 1 1 100.00
hmac_test_hmac384_vectors 16.000s 1457.004us 1 1 100.00
hmac_test_hmac512_vectors 25.000s 2126.793us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 15.000s 1074.886us 1 1 100.00
hmac_long_msg 29.000s 2509.924us 1 1 100.00
hmac_back_pressure 68.000s 1573.908us 1 1 100.00
hmac_datapath_stress 62.000s 1362.377us 1 1 100.00
hmac_burst_wr 31.000s 2176.014us 1 1 100.00
hmac_error 116.000s 4298.819us 1 1 100.00
hmac_wipe_secret 107.000s 9596.726us 1 1 100.00
hmac_test_sha256_vectors 322.000s 29139.998us 1 1 100.00
hmac_test_sha384_vectors 478.000s 14369.800us 1 1 100.00
hmac_test_sha512_vectors 633.000s 72395.056us 1 1 100.00
hmac_test_hmac256_vectors 20.000s 1731.712us 1 1 100.00
hmac_test_hmac384_vectors 16.000s 1457.004us 1 1 100.00
hmac_test_hmac512_vectors 25.000s 2126.793us 1 1 100.00
hmac_stress_all 221.000s 16027.854us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 221.000s 16027.854us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 21.482us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 64.139us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 5.000s 1991.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 5.000s 1991.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 20.661us 1 1 100.00
hmac_csr_rw 2.000s 24.127us 1 1 100.00
hmac_csr_aliasing 2.000s 58.768us 1 1 100.00
hmac_same_csr_outstanding 2.000s 65.923us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 20.661us 1 1 100.00
hmac_csr_rw 2.000s 24.127us 1 1 100.00
hmac_csr_aliasing 2.000s 58.768us 1 1 100.00
hmac_same_csr_outstanding 2.000s 65.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 205.693us 1 1 100.00
hmac_tl_intg_err 2.000s 549.640us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 549.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 15.000s 1074.886us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 72.587us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 111.000s 2457.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 145.414us 1 1 100.00