Simulation Results: lc_ctrl/volatile_unlock_disabled

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.74 %
  • code
  • 90.69 %
  • assert
  • 96.83 %
  • func
  • 78.71 %
  • block
  • 95.94 %
  • line
  • 96.90 %
  • branch
  • 89.66 %
  • toggle
  • 83.35 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
73.33%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 368.648us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 3.000s 21.785us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 3.000s 41.148us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 4.000s 224.424us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 58.420us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 3.000s 26.508us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 3.000s 41.148us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 58.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.000s 321.575us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 23.404us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 27.095us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 2 7 28.57
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3.000s 27.095us 1 1 100.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 8.000s 1913.185us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 5.000s 794.853us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 5.000s 305.670us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.000s 10987.745us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 327.002us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 145.704us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.000s 5845.673us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 148.433us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 43.032us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 268.078us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 208.741us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 848.881us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 36.279us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.458s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 3.000s 81.482us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 28.283us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 28.283us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 3.000s 21.785us 1 1 100.00
lc_ctrl_csr_rw 3.000s 41.148us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 58.420us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 56.706us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 3.000s 21.785us 1 1 100.00
lc_ctrl_csr_rw 3.000s 41.148us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 58.420us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 56.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.000s 227.538us 1 1 100.00
lc_ctrl_tl_intg_err 4.000s 316.707us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 4.000s 316.707us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.000s 321.575us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 227.538us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 227.538us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 227.538us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 227.538us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 227.538us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 227.538us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 227.538us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 227.538us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.000s 1913.185us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 371.189us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1250.403us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1250.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 3007425857926133067976415928216417076252226267808123532007011269565104335181 None
lc_ctrl_state_post_trans 103403066333824706228474956382663074703342887523266042312643723082436175182356 None
lc_ctrl_errors 14102970470978355816009830007418112405663334425124443825529010882001635354932 None
lc_ctrl_jtag_state_failure 100031871694373117466158476035075387253360659515607976800431233124988668092035 None
lc_ctrl_jtag_state_post_trans 62500015958765690572647144264816300675358425886616171158365224795812863681802 None
lc_ctrl_jtag_prog_failure 39364601636544455260056688197333371523410172063348442200689613353934719751014 None
lc_ctrl_jtag_errors 34574982133791767118685624534135707569601015474700970128454376681520313447112 None
lc_ctrl_sec_mubi 39166791206353528690368633338054674643693635585113256806163368356435563233931 None
lc_ctrl_stress_all 83027021181199157109463896445022390921462375274566002230221110731133560187818 None
lc_ctrl_stress_all_with_rand_reset 27328527365372320287183139755669257420565077259617594310125579768670352101972 None