Simulation Results: lc_ctrl/volatile_unlock_enabled

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.54 %
  • code
  • 90.08 %
  • assert
  • 96.83 %
  • func
  • 78.71 %
  • block
  • 96.25 %
  • line
  • 97.12 %
  • branch
  • 90.50 %
  • toggle
  • 79.83 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
76.67%
V2S
80.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 368.374us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 41.861us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.166us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 24.992us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 30.041us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 62.518us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 14.166us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 30.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 68.081us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 461.639us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 98.719us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 8.000s 466.945us 1 1 100.00
lc_ctrl_jtag_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 11 13 84.62
lc_ctrl_jtag_smoke 4.000s 432.913us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.000s 1318.827us 1 1 100.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 5.000s 859.905us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.000s 1324.519us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 248.078us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 252.495us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 3014.427us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 129.704us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 42.361us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 214.565us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 144.241us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 126.570us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 14.715us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.092s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 23.128us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 57.947us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 57.947us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 41.861us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.166us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 30.041us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 76.224us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 41.861us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.166us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 30.041us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 76.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 294.093us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 1027.773us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 1027.773us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 461.639us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 294.093us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 294.093us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 294.093us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 294.093us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 294.093us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 294.093us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 294.093us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 294.093us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.000s 466.945us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 68.081us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.000s 1318.827us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 1089.756us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1277.261us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1277.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 9 test runs
lc_ctrl_state_failure 59563662777281624940643453227248497223744475664118287646822236257891138210537 None
lc_ctrl_prog_failure 100427886643508136615240499722924335142416390011735616343646664158114012386953 None
lc_ctrl_errors 88660985213987492832910891910775193905616794509779790176587742049677096993181 None
lc_ctrl_jtag_state_failure 73566581238423253259805312219760449590452929166382500659773603904065388339871 None
lc_ctrl_jtag_prog_failure 5766262179767540698305160244346350068498743541828822253866662775631333443979 None
lc_ctrl_jtag_errors 93161073096026067188480780257138490351798028907241287892833570693074424556526 None
lc_ctrl_sec_mubi 79007212008805649320131019382635774576535258418856138350151374473519706619302 None
lc_ctrl_stress_all 14463128201983522801633264205605895434285459008126614253790329073317510825771 None
lc_ctrl_stress_all_with_rand_reset 7777531695230062518913016508007811128734349372941872645305066431465316251698 None