Simulation Results: mbx

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.77 %
  • code
  • 87.88 %
  • assert
  • 97.53 %
  • func
  • 74.90 %
  • block
  • 95.99 %
  • line
  • 95.47 %
  • branch
  • 89.37 %
  • toggle
  • 78.80 %
Validation stages
V1
83.33%
V2
90.91%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 35.000s 1510.050us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 18.378us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 14.091us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 504.992us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 23.968us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 2.422us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 14.091us 1 1 100.00
mbx_csr_aliasing 1.000s 23.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 115.000s 32321.443us 1 1 100.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 150.000s 27234.915us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 58.000s 6221.418us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 12.000s 1509.034us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 14.068us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 15.158us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 5.052us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 5.052us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 18.378us 1 1 100.00
mbx_csr_rw 1.000s 14.091us 1 1 100.00
mbx_csr_aliasing 1.000s 23.968us 1 1 100.00
mbx_same_csr_outstanding 1.000s 15.416us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 18.378us 1 1 100.00
mbx_csr_rw 1.000s 14.091us 1 1 100.00
mbx_csr_aliasing 1.000s 23.968us 1 1 100.00
mbx_same_csr_outstanding 1.000s 15.416us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 353.975us 1 1 100.00
mbx_sec_cm 1.000s 65.070us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:718) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 105397887071982905259926317773124424187266929422766817141328141090359315019935 85
TL item was: req: (cip_tl_seq_item@17724) { a_addr: 'hc48d5034 a_data: 'h7ad5272c a_mask: 'ha a_size: 'h2 a_param: 'h0 a_source: 'hf6 a_opcode: 'h1 a_user: 'h27556 d_param: 'h0 d_source: 'hf6 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 5052326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 81376546045109744307793766718871489080762725349883772852578713646115671961830 86
TL item was: req: (cip_tl_seq_item@19619) { a_addr: 'h948c2394 a_data: 'hb017cd53 a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'h85 a_opcode: 'h1 a_user: 'h27f7c d_param: 'h0 d_source: 'h85 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2421717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---