| V1 |
|
100.00% |
| V2 |
|
76.47% |
| V2S |
|
96.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| otbn_smoke | 13.000s | 487.349us | 1 | 1 | 100.00 | |
| otbn_smoke_vectorized | 12.000s | 21.374us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 28.494us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 13.000s | 61.776us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 5.000s | 16.650us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 10.000s | 149.412us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 5.000s | 16.384us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 7.000s | 147.709us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 5.000s | 16.650us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 5.000s | 16.384us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 131.000s | 2910.229us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 19.000s | 174.264us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 33.000s | 222.924us | 1 | 1 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 71.000s | 630.335us | 1 | 1 | 100.00 | |
| wfi | 0 | 3 | 0.00 | |||
| otbn_wfi_smoke | 7.000s | 5.769us | 0 | 1 | 0.00 | |
| otbn_wfi_sec_wipe | 8.000s | 15.415us | 0 | 1 | 0.00 | |
| otbn_wfi_back_to_back | 6.000s | 5.192us | 0 | 1 | 0.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 186.000s | 2371.788us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 212.000s | 1509.625us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 12.000s | 33.207us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 0 | 1 | 0.00 | |||
| otbn_zero_state_err_urnd | 10.000s | 42.399us | 0 | 1 | 0.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 25.000s | 157.254us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 7.000s | 17.671us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 5.000s | 138.645us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 6.000s | 85.633us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 6.000s | 85.633us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 13.000s | 61.776us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 5.000s | 16.650us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 5.000s | 16.384us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 7.000s | 31.485us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 13.000s | 61.776us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 5.000s | 16.650us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 5.000s | 16.384us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 7.000s | 31.485us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 12.000s | 60.207us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 13.000s | 35.437us | 1 | 1 | 100.00 | |
| internal_integrity | 4 | 4 | 100.00 | |||
| otbn_alu_bignum_mod_err | 26.000s | 44.521us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 7.000s | 26.136us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 10.000s | 252.963us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 8.000s | 17.715us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 8.000s | 19.155us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 8.000s | 38.105us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 1 | 1 | 100.00 | |||
| otbn_partial_wipe | 7.000s | 72.874us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| otbn_tl_intg_err | 29.000s | 441.103us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 34.000s | 986.799us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 13.000s | 487.349us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 13.000s | 35.437us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 12.000s | 60.207us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 29.000s | 441.103us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 12.000s | 33.207us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 12.000s | 60.207us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 13.000s | 35.437us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 10.000s | 42.399us | 0 | 1 | 0.00 | |
| otbn_illegal_mem_acc | 8.000s | 19.155us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 28.494us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 12.000s | 60.207us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 13.000s | 35.437us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 10.000s | 42.399us | 0 | 1 | 0.00 | |
| otbn_illegal_mem_acc | 8.000s | 19.155us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 12.000s | 33.207us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 12.000s | 60.207us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 13.000s | 35.437us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 10.000s | 42.399us | 0 | 1 | 0.00 | |
| otbn_illegal_mem_acc | 8.000s | 19.155us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 28.494us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 8.000s | 120.697us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 10.000s | 13.965us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 267.000s | 822.481us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 267.000s | 822.481us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 15.000s | 35.949us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 13.000s | 106.421us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 11.000s | 21.706us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 11.000s | 21.706us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 16.000s | 26.510us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 28.494us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 28.494us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 28.494us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 186.000s | 2371.788us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 28.494us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 28.494us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 9.000s | 32.886us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 11.000s | 28.494us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 262.000s | 3426.345us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 11.000s | 12.441us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. | 2 test runs | |||
| otbn_wfi_smoke | 77847917573079774276902243549846300172686894634324115683007576167328370138738 | 117 |
UVM_INFO @ 5769348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_wfi_back_to_back | 81897571349893015359637985376738414841961450645964282646880383233660699144086 | 109 |
UVM_INFO @ 5191579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 1 test run | |||
| otbn_stress_all_with_rand_reset | 9658900003669839203604433449067406963327799215309881766874212202650843356380 | 147 |
UVM_INFO @ 12441442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed | 1 test run | |||
| otbn_zero_state_err_urnd | 96185785913742430354602044850697988145987081065533439409890947895439340601317 | 109 |
UVM_ERROR @ 42399463 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 42399463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value. | 1 test run | |||
| otbn_wfi_sec_wipe | 22031638333501919402701777574858891147774370261912488135430407782064760179312 | 111 |
UVM_FATAL @ 15415252 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 15415252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|