Simulation Results: otp_ctrl

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.90 %
  • code
  • 71.11 %
  • assert
  • 91.67 %
  • func
  • 52.92 %
  • line
  • 86.70 %
  • branch
  • 81.93 %
  • cond
  • 85.02 %
  • toggle
  • 65.69 %
  • FSM
  • 36.19 %
Validation stages
V1
88.89%
V2
65.00%
V2S
44.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.350s 56.500us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 7.000s 389.619us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 5.220s 1091.524us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.620s 124.628us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.120s 447.322us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.810s 188.283us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.080s 191.968us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.620s 124.628us 1 1 100.00
otp_ctrl_csr_aliasing 2.810s 188.283us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.050s 80.366us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.740s 577.245us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 138.040s 5804.635us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 5.710s 415.235us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 44.400s 11631.233us 1 1 100.00
otp_ctrl_check_fail 12.620s 351.786us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.510s 3014.596us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 5.730s 198.769us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 13.520s 486.305us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 9.610s 1176.617us 1 1 100.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 9.740s 410.318us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 5.580s 1217.047us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 33.930s 13176.345us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 65.860s 5372.575us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.940s 47.707us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.710s 823.861us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.720s 104.062us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.720s 104.062us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 5.220s 1091.524us 1 1 100.00
otp_ctrl_csr_rw 2.620s 124.628us 1 1 100.00
otp_ctrl_csr_aliasing 2.810s 188.283us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.070s 101.858us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 5.220s 1091.524us 1 1 100.00
otp_ctrl_csr_rw 2.620s 124.628us 1 1 100.00
otp_ctrl_csr_aliasing 2.810s 188.283us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.070s 101.858us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
otp_ctrl_tl_intg_err 26.920s 2480.430us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 26.920s 2480.430us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 7.000s 389.619us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 7.000s 389.619us 0 1 0.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
otp_ctrl_macro_errs 5.580s 1217.047us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
otp_ctrl_macro_errs 5.580s 1217.047us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.410s 129.165us 1 1 100.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 5.710s 415.235us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 12.620s 351.786us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 5.730s 198.769us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 5.730s 198.769us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 5.730s 198.769us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 5.730s 198.769us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 5.730s 198.769us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 7.000s 389.619us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 5.730s 198.769us 0 1 0.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 7.000s 389.619us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 306.890s 50921.978us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.510s 3014.596us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 7.000s 389.619us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 7.000s 389.619us 0 1 0.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 5.580s 1217.047us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 119.560s 26176.633us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 35.800s 19240.678us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_smoke 109067329495683059065793249203818529418965108284174494367649266448686291526274 4488
UVM_INFO @ 389618800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_partition_walk 38459588206457997859198517489148880737316074591361519740383457675589610185445 160061
UVM_INFO @ 5804634559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_dai_lock 89932865791187743518881336968743943413710342746329135474811757381213594581376 1272
UVM_INFO @ 198768901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 82134738076972438131445053480030875239051704177583575302490612222368784072069 6276
UVM_INFO @ 410318354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_parallel_key_req 114682296455716352518039163266044211038098110300312147717119401441578380611128 6792
UVM_INFO @ 486305046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33032484006981557194023076415496317818745772605861235275455043009008161149297 2751
UVM_INFO @ 19240677640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 52129441178467707328905694402560396090335325898691476458627025387688244211924 95
UVM_INFO @ 26176633123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 27141347383230247345996419516611734111657916123377725412967982406654050092003 10750
UVM_INFO @ 351786424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
otp_ctrl_macro_errs 23481426986725666451929101831530972532608595295289945378597293499211569391235 2111
UVM_INFO @ 1217047467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_stress_all 75696552351874858441737034108278947548885008802088146987710509837609404627727 36831
UVM_INFO @ 5372574659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_check_error) did not fire in * cycles. 1 test run
otp_ctrl_sec_cm 10729860812899389923605382195204801817192707625430853192545093489151248603602 2583
UVM_INFO @ 50921978328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---