Simulation Results: rom_ctrl/32kb

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.15 %
  • code
  • 78.31 %
  • assert
  • 96.65 %
  • func
  • 71.50 %
  • block
  • 78.24 %
  • line
  • 78.74 %
  • branch
  • 78.60 %
  • toggle
  • 84.48 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
66.67%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 780.642us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 77.503us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 66.795us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 67.296us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 53.173us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 73.297us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 66.795us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 53.173us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 60.899us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 55.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 331.254us 0 1 0.00
stress_all 0 1 0.00
rom_ctrl_stress_all 10801.000s 0.000us 0 1 0.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3601.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 79.477us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 211.137us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 211.137us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 77.503us 1 1 100.00
rom_ctrl_csr_rw 3.000s 66.795us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 53.173us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 66.178us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 77.503us 1 1 100.00
rom_ctrl_csr_rw 3.000s 66.795us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 53.173us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 66.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 76.828us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 131.000s 1425.401us 1 1 100.00
rom_ctrl_tl_intg_err 16.000s 459.499us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 131.000s 1425.401us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 131.000s 1425.401us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 131.000s 1425.401us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 131.000s 1425.401us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 780.642us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 780.642us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 780.642us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 16.000s 459.499us 1 1 100.00
sec_cm_bus_local_esc 0 2 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3601.000s 0.000us 0 1 0.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 76.828us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 131.000s 1425.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 10.000s 351.279us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
rom_ctrl_stress_all 32390266203966935847867315329505038075335498572154427257857993405629362088385 None
rom_ctrl_corrupt_sig_fatal_chk 78657635454362626886941066102079780049331132109236410252688389173169367371042 None
rom_ctrl_kmac_err_chk 53876545563703355074374791202132934194019266139236958427127627309439791188231 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 59493940484518489097322741029117086970446676998996384761371993831959653773236 88
UVM_INFO @ 331254358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 7997872328167003813512077443466222370420042728476783861165505926491389273539 111
UVM_INFO @ 351279190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---