Simulation Results: rom_ctrl/64kb

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.61 %
  • code
  • 79.61 %
  • assert
  • 97.23 %
  • func
  • 85.99 %
  • block
  • 78.32 %
  • line
  • 78.74 %
  • branch
  • 78.84 %
  • toggle
  • 84.69 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 4845.497us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 98.333us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 61.483us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 185.016us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 77.663us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 63.504us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 61.483us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 77.663us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 58.552us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 51.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 9.627us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.000s 206.502us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 10.000s 735.230us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 68.361us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 709.331us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 709.331us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 98.333us 1 1 100.00
rom_ctrl_csr_rw 3.000s 61.483us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 77.663us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 67.520us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 98.333us 1 1 100.00
rom_ctrl_csr_rw 3.000s 61.483us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 77.663us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 67.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 93.229us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 258.000s 2421.621us 1 1 100.00
rom_ctrl_tl_intg_err 58.000s 286.047us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 258.000s 2421.621us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 258.000s 2421.621us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 258.000s 2421.621us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 258.000s 2421.621us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 4845.497us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 4845.497us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 4845.497us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 58.000s 286.047us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 10.000s 735.230us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 93.229us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 258.000s 2421.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 6.000s 304.750us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 107353196338035136198236751929444523394970701797976717812324993792692856800820 88
UVM_INFO @ 9626868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_corrupt_sig_fatal_chk 109530968436214440244388660766016214910607349276406075939346505124209979990757 None
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 26027568222432564568927067948612954898685146525193782973859117823285261007582 90
UVM_INFO @ 304749558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---