Simulation Results: rstmgr

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 99.18 %
  • assert
  • 98.35 %
  • func
  • 92.77 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.30 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.940s 74.593us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.690s 92.872us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.300s 37.553us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.880s 135.866us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.330s 35.430us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.570s 66.669us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.300s 37.553us 1 1 100.00
rstmgr_csr_aliasing 1.330s 35.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.540s 79.697us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.640s 49.231us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.400s 76.931us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 7.450s 660.183us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 7.450s 660.183us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 7.450s 660.183us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 7.450s 660.183us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 10.580s 1320.473us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.200s 45.593us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.440s 61.916us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.440s 61.916us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.690s 92.872us 1 1 100.00
rstmgr_csr_rw 1.300s 37.553us 1 1 100.00
rstmgr_csr_aliasing 1.330s 35.430us 1 1 100.00
rstmgr_same_csr_outstanding 1.410s 40.751us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.690s 92.872us 1 1 100.00
rstmgr_csr_rw 1.300s 37.553us 1 1 100.00
rstmgr_csr_aliasing 1.330s 35.430us 1 1 100.00
rstmgr_same_csr_outstanding 1.410s 40.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 57.990s 6851.503us 1 1 100.00
rstmgr_tl_intg_err 3.890s 331.406us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 57.990s 6851.503us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 57.990s 6851.503us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.890s 331.406us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.770s 66.554us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.460s 422.281us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.480s 291.647us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 57.990s 6851.503us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.300s 37.553us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.300s 37.553us 1 1 100.00