Simulation Results

Simulation Results: rv_dm/use_dmi_interface

03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
86.97 %

code
73.32 %

assert
95.58 %

func
92.02 %

block
89.41 %

line
89.37 %

branch
71.25 %

toggle
70.17 %

FSM
62.50 %

Validation stages

V1		92.59%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	48.000s	2371.223us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	41.000s	402.580us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	51.000s	1110.639us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	51.000s	8622.105us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	46.000s	698.283us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	53.000s	8116.246us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	44.000s	1585.121us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	47.000s	17629.337us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	53.000s	10864.451us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	52.000s	284.994us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	48.000s	514.556us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	48.000s	126.771us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	46.000s	121.589us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	50.000s	216.994us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	52.000s	180.499us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	46.000s	105.066us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	47.000s	398.298us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	52.000s	284.994us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	50.000s	106.540us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	49.000s	1290.778us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	48.000s	126.771us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	47.000s	48.678us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	47.000s	230.495us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	42.000s	158.422us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	104.000s	33694.720us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	66.000s	2417.082us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	42.000s	201.625us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	66.000s	2417.082us	1	1	100.00
	rv_dm_csr_rw	42.000s	158.422us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	43.000s	143.363us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	43.000s	102.637us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	48.000s	2371.223us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	38.000s	259.360us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	42.000s	804.763us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	38.000s	133.397us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	45.000s	657.482us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	46.000s	1977.702us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	47.000s	64.560us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	48.000s	1769.247us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	42.000s	1300.877us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	49.000s	350.693us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	44.000s	1191.747us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	48.000s	166.755us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	49.000s	64.255us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	55.000s	6817.777us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	90.000s	10109.143us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	43.000s	140.551us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	49.000s	665.377us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	45.000s	38.079us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	47.000s	123.086us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	47.000s	123.086us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	66.000s	2417.082us	1	1	100.00
	rv_dm_csr_hw_reset	47.000s	230.495us	1	1	100.00
	rv_dm_csr_rw	42.000s	158.422us	1	1	100.00
	rv_dm_same_csr_outstanding	53.000s	509.472us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	66.000s	2417.082us	1	1	100.00
	rv_dm_csr_hw_reset	47.000s	230.495us	1	1	100.00
	rv_dm_csr_rw	42.000s	158.422us	1	1	100.00
	rv_dm_same_csr_outstanding	53.000s	509.472us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	50.000s	451.894us	1	1	100.00
	rv_dm_tl_intg_err	44.000s	2004.926us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	44.000s	2004.926us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	44.000s	1191.747us	1	1	100.00
	rv_dm_debug_disabled	45.000s	66.834us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	44.000s	1191.747us	1	1	100.00
	rv_dm_debug_disabled	45.000s	66.834us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	48.000s	2371.223us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	39.000s	157.208us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	47.000s	134.997us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	47.000s	134.997us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	39.000s	157.208us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	74.000s	2165.565us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	631.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				3 test runs
	rv_dm_sba_tl_access	44069274736848371198269087922092259632973770311812984517589982139869877382462	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23880
	rv_dm_bad_sba_tl_access	26885058038987883571387111573405132772728146280742766567949953488046792319356	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24033
	rv_dm_autoincr_sba_tl_access	114675438076929158990572705484320119283284850944014246256402893243599581793885	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23902
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	97909844524081016397530314967949173718432561067766410107147070921452375114483	87	UVM_INFO @ 121589474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	32970709244981285627679073001039198956651750033137548679781590379091565376103	159	UVM_INFO @ 2165564646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	28863948571452402180551471911422439551008490049578217853565145878927793295934	87	UVM_INFO @ 350692717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	78797739970436497584046107172393615794112664810248364881004362982224052140650	88	UVM_INFO @ 665377179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	101457680527842019292840754262437488258866187063750732957903791063403849327839	107	UVM_INFO @ 64560432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	72965532666783516034272639768975562314646963532117570889005374621995717254561	87	UVM_INFO @ 64254796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23867) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	80740256885018759345495359316713742083149550624459023905120977688021111248079	87	). UVM_INFO @ 48677576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	93643246929641696341827220715034363448071652848847446687267877277205941018404	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---