| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 1 | 1 | 100.00 | |||
| rv_timer_random | 2.000s | 277.133us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 1.000s | 45.368us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_timer_csr_rw | 1.000s | 13.460us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 5.000s | 1752.459us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.000s | 71.574us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.000s | 19.901us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_timer_csr_rw | 1.000s | 13.460us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 1.000s | 71.574us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 1 | 100.00 | |||
| rv_timer_random_reset | 2.000s | 139.677us | 1 | 1 | 100.00 | |
| disabled | 1 | 1 | 100.00 | |||
| rv_timer_disabled | 2.000s | 57.453us | 1 | 1 | 100.00 | |
| cfg_update_on_fly | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 483.000s | 1466799.151us | 1 | 1 | 100.00 | |
| no_interrupt_test | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 483.000s | 1466799.151us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| rv_timer_stress_all | 14.000s | 6009.417us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_timer_alert_test | 1.000s | 13.274us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| rv_timer_intr_test | 1.000s | 14.545us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 4.000s | 570.519us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 4.000s | 570.519us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 1.000s | 45.368us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 1.000s | 13.460us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 1.000s | 71.574us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.000s | 117.762us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 1.000s | 45.368us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 1.000s | 13.460us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 1.000s | 71.574us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.000s | 117.762us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_timer_sec_cm | 1.000s | 713.496us | 1 | 1 | 100.00 | |
| rv_timer_tl_intg_err | 2.000s | 52.868us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_timer_tl_intg_err | 2.000s | 52.868us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 1 | 1 | 100.00 | |||
| rv_timer_min | 1.000s | 21.069us | 1 | 1 | 100.00 | |
| max_value | 1 | 1 | 100.00 | |||
| rv_timer_max | 1.000s | 97.774us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_stress_all_with_rand_reset | 41.000s | 19451.788us | 1 | 1 | 100.00 | |