Simulation Results: spi_device/1r1w

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.14 %
  • code
  • 89.51 %
  • assert
  • 95.02 %
  • func
  • 67.89 %
  • block
  • 98.33 %
  • line
  • 98.75 %
  • branch
  • 96.96 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 126.000s 17609.297us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 3.000s 171.717us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 131.848us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.000s 285.457us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 3.000s 213.537us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 99.380us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 131.848us 1 1 100.00
spi_device_csr_aliasing 3.000s 213.537us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 33.469us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 27.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 22.814us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 1.391us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.060us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 38.193us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 38.193us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 27.000s 14236.964us 1 1 100.00
spi_device_tpm_sts_read 2.000s 253.647us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 59.000s 9343.516us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 42.000s 4617.018us 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.000s 432.879us 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.000s 432.879us 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 24.000s 1243.592us 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 24.000s 1243.592us 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 24.000s 1243.592us 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 24.000s 1243.592us 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 24.000s 1243.592us 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 7.000s 1098.746us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 20.000s 821.202us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 20.000s 821.202us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 20.000s 821.202us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.000s 282.579us 1 1 100.00
spi_device_read_buffer_direct 5.000s 394.445us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 20.000s 821.202us 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 2.000s 16.607us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.000s 1520.233us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.000s 1520.233us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 241.000s 128253.493us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 126.000s 17609.297us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 116.000s 7940.085us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 493.000s 155659.709us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 146.321us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 210.217us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 8.000s 976.868us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 8.000s 976.868us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 171.717us 1 1 100.00
spi_device_csr_rw 3.000s 131.848us 1 1 100.00
spi_device_csr_aliasing 3.000s 213.537us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 61.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 171.717us 1 1 100.00
spi_device_csr_rw 3.000s 131.848us 1 1 100.00
spi_device_csr_aliasing 3.000s 213.537us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 61.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 68.225us 1 1 100.00
spi_device_tl_intg_err 13.000s 1231.506us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 13.000s 1231.506us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 59634215116196226646954400057849822118515059047016210107641734925935291219661 87
UVM_ERROR @ 1118132 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[998] not found within the scope .
UVM_ERROR @ 1118132 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[998] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 115463006495374623975831374846109643048888970438993226619596013267509529547928 85
UVM_ERROR @ 842368 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x20e [1000001110] vs 0x0 [0])
UVM_ERROR @ 927368 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2bb [1010111011] vs 0x0 [0])
UVM_ERROR @ 930368 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x183 [110000011] vs 0x0 [0])
UVM_ERROR @ 940368 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1fe [111111110] vs 0x0 [0])