Simulation Results: sram_ctrl/main

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 94.56 %
  • code
  • 94.32 %
  • assert
  • 97.01 %
  • func
  • 92.35 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 90.91 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 723.502us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 36.355us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.467us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 219.108us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.913us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 685.672us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 41.467us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.913us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 159.000s 22203.677us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 59.000s 10432.019us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 42.000s 5990.470us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 174.000s 20459.380us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 171.000s 4452.031us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 82.000s 14233.419us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 45.000s 24702.929us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 50.000s 29142.503us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.000s 694.652us 1 1 100.00
sram_ctrl_partial_access_b2b 206.000s 9873.774us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 2772.950us 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.000s 683.803us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 2658.088us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 13.000s 1361.084us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 358.675us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 6.000s 723.502us 1 1 100.00
sram_ctrl_partial_access 6.000s 694.652us 1 1 100.00
sram_ctrl_access_during_key_req 82.000s 14233.419us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 231.000s 13376.890us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 18.462us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 415.768us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 415.768us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 36.355us 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.467us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.913us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.997us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 36.355us 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.467us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.913us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 14790.987us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1295.798us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 262.060us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1295.798us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 262.060us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 1361.084us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 1361.084us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.467us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 50.000s 29142.503us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 50.000s 29142.503us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 50.000s 29142.503us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 45.000s 24702.929us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 14790.987us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 723.502us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 723.502us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 50.000s 29142.503us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1295.798us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 45.000s 24702.929us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1295.798us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1295.798us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 723.502us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1295.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 9.000s 1623.064us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 98464661645766013123928167119378150363505263740695313112185062594093520177833 None
sram_ctrl_mubi_enc_err 1177837715771318994720380040471466344092115373343225964145459923298450706439 None