Simulation Results: sram_ctrl/ret

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.72 %
  • code
  • 81.71 %
  • assert
  • 97.26 %
  • func
  • 93.20 %
  • block
  • 92.12 %
  • line
  • 93.78 %
  • branch
  • 88.07 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 173.636us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 22.391us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.948us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 129.208us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.731us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 274.060us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 17.948us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.731us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 11.000s 2611.748us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 6.000s 361.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 252.723us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 150.000s 9188.622us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 1136.479us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 265.933us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 300.377us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 1182.909us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 232.275us 1 1 100.00
sram_ctrl_partial_access_b2b 93.000s 1813.697us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 123.611us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 45.044us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 101.397us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 1492.185us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 73.178us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 3.000s 173.636us 1 1 100.00
sram_ctrl_partial_access 2.000s 232.275us 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 265.933us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 30.000s 1252.499us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 43.662us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 99.928us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 99.928us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 22.391us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.948us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.731us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 94.575us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 22.391us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.948us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.731us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 94.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1391.517us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 208.664us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 275.343us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 208.664us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 275.343us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 1492.185us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 1492.185us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.948us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1182.909us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1182.909us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1182.909us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 300.377us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1391.517us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 173.636us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 173.636us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 1182.909us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 208.664us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 300.377us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 208.664us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 208.664us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 173.636us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 208.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 40.000s 1471.205us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 74478569324945774508262513798039436365886740653743982545323304281149187888698 None
sram_ctrl_mubi_enc_err 24157788263898922452431339489442971610362045490263730259155447511001099212392 None