Simulation Results: uart

 
03/09/2026 16:40:21 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 93.45 %
  • code
  • 92.53 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 6.000s 927.946us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 56.054us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 2.000s 14.027us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 49.274us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 52.182us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 25.844us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 2.000s 14.027us 1 1 100.00
uart_csr_aliasing 1.000s 52.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 107.000s 164570.767us 1 1 100.00
parity 2 2 100.00
uart_smoke 6.000s 927.946us 1 1 100.00
uart_tx_rx 107.000s 164570.767us 1 1 100.00
parity_error 2 2 100.00
uart_intr 17.000s 7151.279us 1 1 100.00
uart_rx_parity_err 32.000s 41126.969us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 107.000s 164570.767us 1 1 100.00
uart_intr 17.000s 7151.279us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 54.000s 90663.899us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 36.000s 89780.136us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 147.000s 102860.376us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 17.000s 7151.279us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 17.000s 7151.279us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 17.000s 7151.279us 1 1 100.00
perf 1 1 100.00
uart_perf 224.000s 37311.365us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 6.000s 8296.492us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 6.000s 8296.492us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 11.000s 6454.872us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.000s 3188.918us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 1054.135us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 22.000s 3374.832us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 658.000s 107505.305us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 256.000s 216820.321us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 2.000s 24.137us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 46.594us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 131.874us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 131.874us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 56.054us 1 1 100.00
uart_csr_rw 2.000s 14.027us 1 1 100.00
uart_csr_aliasing 1.000s 52.182us 1 1 100.00
uart_same_csr_outstanding 1.000s 58.493us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 56.054us 1 1 100.00
uart_csr_rw 2.000s 14.027us 1 1 100.00
uart_csr_aliasing 1.000s 52.182us 1 1 100.00
uart_same_csr_outstanding 1.000s 58.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 252.325us 1 1 100.00
uart_tl_intg_err 1.000s 52.693us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 52.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 12.000s 1018.216us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 26938788304488730925394194307015013861505613042805833608477207394187856293871 83
UVM_ERROR @ 16721539 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 25871539 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 36061539 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 238701539 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0