Simulation Results: ac_range_check

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.86 %
  • code
  • 93.03 %
  • assert
  • 97.75 %
  • func
  • 57.79 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 43.000s 1447.762us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 48.000s 750.226us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 9.000s 21.528us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 10.000s 21.304us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 38.000s 737.493us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 13.000s 274.904us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 9.000s 29.239us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 10.000s 21.304us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 274.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 9.000s 26.902us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 54.000s 1529.928us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 155.000s 5225.441us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 9.000s 22.121us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 10.000s 14.594us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 9.000s 203.467us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 9.000s 203.467us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 9.000s 21.528us 1 1 100.00
ac_range_check_csr_rw 10.000s 21.304us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 274.904us 1 1 100.00
ac_range_check_same_csr_outstanding 11.000s 355.702us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 9.000s 21.528us 1 1 100.00
ac_range_check_csr_rw 10.000s 21.304us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 274.904us 1 1 100.00
ac_range_check_same_csr_outstanding 11.000s 355.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 20.000s 394.435us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 20.000s 394.435us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 20.000s 394.435us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 20.000s 394.435us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 89.000s 3630.688us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 8.000s 34.721us 1 1 100.00
ac_range_check_tl_intg_err 11.000s 473.052us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 345.000s 46734.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 33.000s 2387.141us 1 1 100.00