Simulation Results: aes/gcm_unmasked

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.73 %
  • code
  • 91.00 %
  • assert
  • 97.75 %
  • func
  • 65.43 %
  • block
  • 91.14 %
  • line
  • 92.61 %
  • branch
  • 84.74 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 61.298us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 126.679us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 77.865us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 116.471us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 1544.238us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 66.045us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 69.336us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 116.471us 1 1 100.00
aes_csr_aliasing 2.000s 66.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 126.679us 1 1 100.00
aes_config_error 3.000s 121.805us 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 126.679us 1 1 100.00
aes_config_error 3.000s 121.805us 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 84.699us 1 1 100.00
aes_b2b 8.000s 460.600us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 126.679us 1 1 100.00
aes_config_error 3.000s 121.805us 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
aes_alert_reset 3.000s 84.796us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 66.013us 1 1 100.00
aes_config_error 3.000s 121.805us 1 1 100.00
aes_alert_reset 3.000s 84.796us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 152.491us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 1111.664us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 84.796us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 84.699us 1 1 100.00
aes_sideload 3.000s 119.674us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 76.607us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10801.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 3.000s 56.814us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 99.120us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 99.120us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 77.865us 1 1 100.00
aes_csr_rw 3.000s 116.471us 1 1 100.00
aes_csr_aliasing 2.000s 66.045us 1 1 100.00
aes_same_csr_outstanding 2.000s 105.095us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 77.865us 1 1 100.00
aes_csr_rw 3.000s 116.471us 1 1 100.00
aes_csr_aliasing 2.000s 66.045us 1 1 100.00
aes_same_csr_outstanding 2.000s 105.095us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 85.470us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 4.000s 93.792us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 58.339us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 77.005us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 77.005us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 77.005us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 77.005us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 134.742us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1413.762us 1 1 100.00
aes_tl_intg_err 4.000s 1728.615us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 1728.615us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 84.796us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 77.005us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 77.005us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 126.679us 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
aes_alert_reset 3.000s 84.796us 1 1 100.00
aes_core_fi 4.000s 66.133us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 121.805us 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
aes_core_fi 4.000s 66.133us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 77.005us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 68.850us 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 84.699us 1 1 100.00
aes_sideload 3.000s 119.674us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 68.850us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 68.850us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 68.850us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 68.850us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 68.850us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 84.699us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 93.792us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 4.000s 93.792us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 58.339us 1 1 100.00
aes_ctr_fi 2.000s 49.723us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 93.792us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 4.000s 93.792us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 58.339us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 58.339us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 93.792us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 4.000s 93.792us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 49.723us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 93.792us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 4.000s 93.792us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 58.339us 1 1 100.00
aes_ctr_fi 2.000s 49.723us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 84.796us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 4.000s 93.792us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 58.339us 1 1 100.00
aes_ctr_fi 2.000s 49.723us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 4.000s 93.792us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 58.339us 1 1 100.00
aes_ctr_fi 2.000s 49.723us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 4.000s 93.792us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 49.723us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 93.792us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 4.000s 93.792us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 58.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 16.000s 3950.504us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
aes_control_fi 94954260803395057825781192092764127109411986539746748756265108406281271522764 None
aes_stress_all 105557209871508393174680780832322640092720282548393965397907867121844416405808 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 18410046393564731734492819597482248777268790395419131818148785095215604925189 2494
UVM_INFO @ 85469918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 76089421591951194343270279714157669347626237024146550489204711543061423793513 6662
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 113525377422024821608164904397835694801476983069494243360608992041843604683397 647
UVM_INFO @ 3950504317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---