Simulation Results: alert_handler

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.81 %
  • code
  • 89.58 %
  • assert
  • 97.93 %
  • func
  • 75.92 %
  • line
  • 99.70 %
  • branch
  • 98.28 %
  • cond
  • 91.67 %
  • toggle
  • 82.42 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 21.080s 852.196us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 2.940s 42.374us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 6.050s 72.410us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 373.770s 12286.039us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 32.650s 897.501us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.830s 75.892us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 6.050s 72.410us 1 1 100.00
alert_handler_csr_aliasing 32.650s 897.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 116.850s 11780.461us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 85.050s 4928.020us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 822.430s 31742.831us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 24.340s 1302.097us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 21.080s 852.196us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 23.610s 920.067us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 65.050s 1178.568us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 85.340s 4344.309us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 987.220s 74193.263us 1 1 100.00
alert_handler_lpg_stub_clk 859.910s 11095.787us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 367.620s 4293.182us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 9.930s 166.154us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.330s 24.433us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.660s 15.933us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 23.880s 993.378us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 23.880s 993.378us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 2.940s 42.374us 1 1 100.00
alert_handler_csr_rw 6.050s 72.410us 1 1 100.00
alert_handler_csr_aliasing 32.650s 897.501us 1 1 100.00
alert_handler_same_csr_outstanding 23.690s 743.428us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 2.940s 42.374us 1 1 100.00
alert_handler_csr_rw 6.050s 72.410us 1 1 100.00
alert_handler_csr_aliasing 32.650s 897.501us 1 1 100.00
alert_handler_same_csr_outstanding 23.690s 743.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 211.870s 4940.892us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 211.870s 4940.892us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 211.870s 4940.892us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 211.870s 4940.892us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 646.140s 19644.373us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
alert_handler_tl_intg_err 111.910s 2713.793us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 111.910s 2713.793us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 211.870s 4940.892us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 21.080s 852.196us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 21.080s 852.196us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 21.080s 852.196us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 21.080s 852.196us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.340s 1302.097us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 987.220s 74193.263us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.340s 1302.097us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 822.430s 31742.831us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 822.430s 31742.831us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 11.290s 671.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 222.140s 5396.945us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 113984447696048970588111838054183343880515357835042602529275174971381393743612 150
UVM_INFO @ 166153855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 86215105125292358233392015419606556058114179940721086068644716130997032560930 144
UVM_INFO @ 5396945349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---