Simulation Results: clkmgr

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.24 %
  • code
  • 69.85 %
  • assert
  • 90.08 %
  • func
  • 74.80 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 79.79 %
  • toggle
  • 99.62 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.420s 31.733us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.860s 19.135us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.750s 4.630us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 3.660s 293.065us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.920s 19.289us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.740s 102.384us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.750s 4.630us 0 1 0.00
clkmgr_csr_aliasing 0.920s 19.289us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.270s 20.874us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.220s 26.064us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.870s 14.738us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.420s 31.733us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.850s 7.589us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.700s 6.780us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.850s 7.589us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.850s 145.730us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.830s 13.732us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 5.670s 269.759us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 5.670s 269.759us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.860s 19.135us 1 1 100.00
clkmgr_csr_rw 0.750s 4.630us 0 1 0.00
clkmgr_csr_aliasing 0.920s 19.289us 0 1 0.00
clkmgr_same_csr_outstanding 0.850s 4.046us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.860s 19.135us 1 1 100.00
clkmgr_csr_rw 0.750s 4.630us 0 1 0.00
clkmgr_csr_aliasing 0.920s 19.289us 0 1 0.00
clkmgr_same_csr_outstanding 0.850s 4.046us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 7.740s 478.911us 1 1 100.00
clkmgr_tl_intg_err 1.080s 10.861us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 65.821us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 65.821us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 65.821us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 65.821us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.790s 56.973us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.080s 10.861us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.850s 7.589us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.700s 6.780us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.750s 65.821us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.010s 72.221us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.750s 4.630us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 7.740s 478.911us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.750s 4.630us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.750s 4.630us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 7.740s 478.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.880s 3.586us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.230s 50.089us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 4 test runs
clkmgr_shadow_reg_errors_with_csr_rw 2105043776523278891347082569646285980628248789116764088667736037807623970463 81
UVM_INFO @ 56972547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 109136964788415174998406457720786712543701669577464991442792053606503478075487 103
UVM_INFO @ 10861279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 917612658134408429792106008538203860368962284326559268005907845635366202760 81
UVM_INFO @ 4629946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 113610819654471252556787025904038361897541312178965462437721552822872889723740 87
UVM_INFO @ 19289356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 86160837640194842692291875189331380090104771974775933064516741030224394153529 84
UVM_INFO @ 6779946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 105754708188667758796699849429943015744289992904111167225188469917767282668178 85
UVM_INFO @ 50089477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 75105194073058445479494326095206099516238900995128677189188972283986727393692 135
UVM_INFO @ 145729967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 19642563491808205862790440784206395695268300760195271671942435494061367234986 82
UVM_INFO @ 7589049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 13618204453608239426251012014894461924619086535835150770478521812833179179645 80
UVM_INFO @ 3586310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 8336890853675366508768937167188913856618208079690817563538700361972697300438 81
UVM_INFO @ 293065408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 37861750121733210592632799594013515896278898404476602381292216588700576904 81
UVM_INFO @ 4045532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---