Simulation Results: csrng

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 85.12 %
  • code
  • 91.89 %
  • assert
  • 93.01 %
  • func
  • 70.46 %
  • block
  • 96.52 %
  • line
  • 97.27 %
  • branch
  • 91.34 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 4.000s 83.011us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 24.026us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 20.285us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 6.000s 87.411us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 174.160us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 53.795us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 20.285us 1 1 100.00
csrng_csr_aliasing 4.000s 174.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
alerts 1 1 100.00
csrng_alert 6.000s 97.993us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 17.000s 578.537us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 17.000s 578.537us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 3.000s 34.128us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 14.540us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 22.450us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 138.564us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 138.564us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 24.026us 1 1 100.00
csrng_csr_rw 2.000s 20.285us 1 1 100.00
csrng_csr_aliasing 4.000s 174.160us 1 1 100.00
csrng_same_csr_outstanding 2.000s 76.429us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 24.026us 1 1 100.00
csrng_csr_rw 2.000s 20.285us 1 1 100.00
csrng_csr_aliasing 4.000s 174.160us 1 1 100.00
csrng_same_csr_outstanding 2.000s 76.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 45.255us 1 1 100.00
csrng_tl_intg_err 4.000s 67.289us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 40.574us 1 1 100.00
csrng_csr_rw 2.000s 20.285us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 6.000s 97.993us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 3.000s 34.128us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
csrng_sec_cm 3.000s 45.255us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
csrng_sec_cm 3.000s 45.255us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
csrng_sec_cm 3.000s 45.255us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
csrng_sec_cm 3.000s 45.255us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
csrng_sec_cm 3.000s 45.255us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 6.000s 97.993us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 3.000s 34.128us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 6.000s 97.993us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 67.289us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
csrng_sec_cm 3.000s 45.255us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
csrng_sec_cm 3.000s 45.255us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 119.805us 1 1 100.00
csrng_err 2.000s 18.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 150.000s 6833.832us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:173) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 95292223523325020101501638398832320396296457552267019123412746058026679562896 181
UVM_INFO @ 6833832307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---