Simulation Results: dma

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.20 %
  • code
  • 90.73 %
  • assert
  • 96.50 %
  • func
  • 62.36 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 354.009us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 2494.858us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 2108.834us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 57.981us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 21.287us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 730.401us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 80.753us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 104.755us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 21.287us 1 1 100.00
dma_csr_aliasing 2.000s 80.753us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 63.000s 20166.632us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 1089.000s 85201.603us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 150.000s 8806.155us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 150.000s 8806.155us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 1089.000s 85201.603us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 174.000s 10148.064us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 150.000s 8806.155us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 10.000s 1346.178us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 371.000s 83479.901us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 22.466us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 16.372us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 247.937us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 247.937us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 57.981us 1 1 100.00
dma_csr_rw 2.000s 21.287us 1 1 100.00
dma_csr_aliasing 2.000s 80.753us 1 1 100.00
dma_same_csr_outstanding 3.000s 104.231us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 57.981us 1 1 100.00
dma_csr_rw 2.000s 21.287us 1 1 100.00
dma_csr_aliasing 2.000s 80.753us 1 1 100.00
dma_same_csr_outstanding 3.000s 104.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 20.000s 1221.070us 1 1 100.00
dma_generic_stress 174.000s 10148.064us 1 1 100.00
dma_handshake_stress 150.000s 8806.155us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 1207.294us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 1869.362us 1 1 100.00
dma_sec_cm 2.000s 82.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 136.000s 10221.704us 1 1 100.00
dma_longer_transfer 3.000s 245.471us 1 1 100.00
dma_stress_all_with_rand_reset 12.000s 3290.701us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 56097309298402699795629144852803416001398464284482336567523340468576300602457 114
UVM_INFO @ 3290700876ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---