Simulation Results: edn/edn0

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 75.00 %
  • code
  • 82.60 %
  • assert
  • 93.58 %
  • func
  • 48.81 %
  • block
  • 93.47 %
  • line
  • 96.59 %
  • branch
  • 85.98 %
  • toggle
  • 70.32 %
  • FSM
  • 77.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 17.831us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 57.936us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 15.193us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 163.256us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 23.888us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 18.986us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 15.193us 1 1 100.00
edn_csr_aliasing 2.000s 23.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 131.793us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 131.793us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 131.793us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 38.648us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 45.953us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 20.057us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 43.210us 1 1 100.00
edn_disable_auto_req_mode 2.000s 104.515us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 10.000s 527.680us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 23.762us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 50.996us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 5.000s 551.007us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 5.000s 551.007us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 57.936us 1 1 100.00
edn_csr_rw 2.000s 15.193us 1 1 100.00
edn_csr_aliasing 2.000s 23.888us 1 1 100.00
edn_same_csr_outstanding 2.000s 58.705us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 57.936us 1 1 100.00
edn_csr_rw 2.000s 15.193us 1 1 100.00
edn_csr_aliasing 2.000s 23.888us 1 1 100.00
edn_same_csr_outstanding 2.000s 58.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.000s 3004.810us 1 1 100.00
edn_tl_intg_err 3.000s 165.730us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 25.667us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 45.953us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.000s 3004.810us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.000s 3004.810us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.000s 3004.810us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.000s 3004.810us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 45.953us 1 1 100.00
edn_sec_cm 10.000s 3004.810us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 45.953us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 165.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 31.000s 1548.253us 1 1 100.00