Simulation Results: edn/edn1

 
07/09/2026 15:31:36 DVSim: v1.52.1 sha: 6cca8d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.90 %
  • code
  • 81.05 %
  • assert
  • 97.66 %
  • func
  • 78.99 %
  • line
  • 97.72 %
  • branch
  • 92.21 %
  • cond
  • 88.85 %
  • toggle
  • 86.71 %
  • FSM
  • 39.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.120s 75.256us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.170s 13.856us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.180s 16.103us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.800s 158.141us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.180s 21.823us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.860s 82.581us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.180s 16.103us 1 1 100.00
edn_csr_aliasing 1.180s 21.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.260s 52.837us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.260s 52.837us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.260s 52.837us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.330s 21.017us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.580s 32.353us 1 1 100.00
errs 1 1 100.00
edn_err 1.060s 28.211us 1 1 100.00
disable 2 2 100.00
edn_disable 1.210s 14.397us 1 1 100.00
edn_disable_auto_req_mode 1.560s 134.538us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.140s 470.450us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.040s 28.723us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.150s 50.241us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.750s 48.223us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.750s 48.223us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.170s 13.856us 1 1 100.00
edn_csr_rw 1.180s 16.103us 1 1 100.00
edn_csr_aliasing 1.180s 21.823us 1 1 100.00
edn_same_csr_outstanding 1.770s 121.996us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.170s 13.856us 1 1 100.00
edn_csr_rw 1.180s 16.103us 1 1 100.00
edn_csr_aliasing 1.180s 21.823us 1 1 100.00
edn_same_csr_outstanding 1.770s 121.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.780s 796.468us 1 1 100.00
edn_tl_intg_err 1.840s 212.039us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.250s 16.131us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.580s 32.353us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 796.468us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 796.468us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 796.468us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 796.468us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.580s 32.353us 1 1 100.00
edn_sec_cm 3.780s 796.468us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.580s 32.353us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.840s 212.039us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 43.580s 3916.566us 1 1 100.00